一个5ns访问时间64Kb ECL RAM

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1987.1157113

T. Awaya, K. Toyoda, O. Nomura, Y. Nakaya, K. Tanaka, H. Sugawara

{"title":"一个5ns访问时间64Kb ECL RAM","authors":"T. Awaya, K. Toyoda, O. Nomura, Y. Nakaya, K. Tanaka, H. Sugawara","doi":"10.1109/ISSCC.1987.1157113","DOIUrl":null,"url":null,"abstract":"An 8K×8 bipolar ECL RAM with segmented bit lines and Darlington drive circuits will be described. RAM uses the sharing signal line technique. Wafer process yield is obtained by use of a memory cell with deep P-well base diffusion and two row redundancy.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"58 2","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"A 5ns access time 64Kb ECL RAM\",\"authors\":\"T. Awaya, K. Toyoda, O. Nomura, Y. Nakaya, K. Tanaka, H. Sugawara\",\"doi\":\"10.1109/ISSCC.1987.1157113\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An 8K×8 bipolar ECL RAM with segmented bit lines and Darlington drive circuits will be described. RAM uses the sharing signal line technique. Wafer process yield is obtained by use of a memory cell with deep P-well base diffusion and two row redundancy.\",\"PeriodicalId\":102932,\"journal\":{\"name\":\"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"58 2\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1987.1157113\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1987.1157113","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 14

摘要

将描述具有分段位线和达灵顿驱动电路的8K×8双极ECL RAM。RAM采用共享信号线技术。晶圆制程产率采用深p阱扩散和两行冗余的存储单元。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A 5ns access time 64Kb ECL RAM

An 8K×8 bipolar ECL RAM with segmented bit lines and Darlington drive circuits will be described. RAM uses the sharing signal line technique. Wafer process yield is obtained by use of a memory cell with deep P-well base diffusion and two row redundancy.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

自引率

0.00%

发文量