A four quadrant MOS analog multiplier

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1987.1157181

J. Pena-Finol, J. Connelly

引用次数: 7

Abstract

An MOS analog multiplier based on the square law algebraic identity will be covered. The multiplier achieves a nonlinearity of 9.44%, a bandwidth of 5MHz, dynamic range of 87dB and total harmonic distortion of 0.59%. The chip was fabricated with a 5μm P-well CMOS process. Size is 500mil2and total power consumption is 10mW.

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四象限MOS模拟倍增器

一个基于平方律代数恒等式的MOS模拟乘法器将被覆盖。该乘法器的非线性度为9.44%，带宽为5MHz，动态范围为87dB，总谐波失真为0.59%。该芯片采用5μm p阱CMOS工艺制备。尺寸500mw，总功耗10mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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