An experimental 35ns 1Mb biCMOS DRAM

Abstract

AN EXPERIMENTAL I Rlb bipolar CMOS (Hi-BiCMOS) DRAM with a typical access time of 35ns and typical power dissipation of 450mW at a 60ns cycle time, will be reported. The key to achieving high-speed DRAMs is to introduce high performance bipolar transistors, while maintaining high soft-error immunity, low-power dissipation and low-peak current, even at cycle times shorter than 100ns. Four developments are proposed to meet these requirements: a Hi-BiCMOS DRAM device structure', a high-speed bipolar circuitry combined with a highspeed memory array configuration, a BiCMOS clock driver suitable for an owchip voltage limiter and a current mirror circuit combined with a voltage limiter. Figure 1 shows a Hi-BiCMOS DRAM device structure with twin wells formed in a 1.5pm epitaxial layer. This structure realizes a high fT because the bipolar transistors used have an optimum emitter width of 3 p . In addition, the elimination of the P t buried layer results in a low threshold voltage sensitivity to the substrate bias for NMOSTs in the peripheral circuitry. The'se characteristics are essential for high-speed operation. The bipolar transistor emitters are formed concurrently with the sources and drains of the NMOST. Thus, the fabrication process is almost fully compatible with the conventional CMOS DKARiI; only three additional masking steps are required. The planar cell is formed just above the P+ buried layer to provide high soft error immunity.