{"title":"A GaAs 1K SRAM with 2ns cycle time","authors":"B. Gabillard, C. Rocher, T. Ducourant, M. Prost","doi":"10.1109/ISSCC.1987.1157128","DOIUrl":null,"url":null,"abstract":"An ECL compatible SRAM that attains rise and fall times of 200ps with a power consumtpion of 210mW will be described. Word line clamping and data bus delay reduction allow control of the access time in spite of threshold voltage varation of 90mV.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"110 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1987.1157128","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
An ECL compatible SRAM that attains rise and fall times of 200ps with a power consumtpion of 210mW will be described. Word line clamping and data bus delay reduction allow control of the access time in spite of threshold voltage varation of 90mV.