一个90ns 4Mb的DRAM在一个300mil DIP

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1987.1157143

K. Mashiko, M. Nagatomo, K. Arimoto, Y. Matsuda, K. Furutani, T. Matsukawa, T. Yoshihara, T. Nakano

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引用次数: 12

摘要

本文将描述一种采用2μm深沟槽的折叠位线自适应边壁隔离电容电池的4Mb DRAM，芯片尺寸为72.3mm2，访问时间为90ns。还包含了用于4Mb×1或1Mb×4组织以及静态列或页面模式操作的完整绑定选项。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 90ns 4Mb DRAM in a 300 mil DIP

A 4Mb DRAM employing a folded-bitline adaptive sidewall - isolated capacitance cell with 2μm deep trenches, a 72.3mm2chip size and 90ns access time will be described. Also incorporated are full bonding options for 4Mb×1 or 1Mb×4 organizations and for static column or page-mode operation.

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来源期刊

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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