带有内部刷新的256K CMOS SRAM

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1987.1157079

S. Hanamura, O. Minato, T. Masuhara, Y. Sakai, T. Yamanaka, N. Moriwaki, F. Kojima

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引用次数: 3

摘要

采用0.8μm CMOS技术，单元尺寸为39.2μm2的4晶体管开关电容负载SRAM将被报道。这种方法可以在不损失内部刷新时间的情况下进行访问。接入时间为43ns，待机功率为3.3μW。

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A 256K CMOS SRAM with internal refresh

A four-transistor switched-capacitor load SRAM employing 0.8μm CMOS technology with a cell size of 39.2μm2will be reported. The approach makes it possible to access without time-loss for internal refresh. Access time is 43ns and standby power is 3.3μW.

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1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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