用于数字用户环路的160Kb/s收发器

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1987.1157191

D. Sallaerts, R. Dierckx, M. Rahier

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引用次数: 2

摘要

本报告将描述一种基于回声消除、分组码和单波特采样技术的收发器的实现。在8km以内的环路上获得了低于10-7的误码率。在2μm CMOS上的数字实现导致了45mm2的芯片面积。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 160Kb/s transceiver for digital subscriber loop

This report will describe the implementation of a transceiver based on echo-cancelling, block code and single baud sampling techniques. A BER lower than 10-7has been obtained on loops up to 8km. The digital implementation in 2μm CMOS has resulted in a 45mm2chip area.

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来源期刊

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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