A 32b CMOS microprocessor with on-chip instruction and data caching and memory management

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1987.1157147

D. Archer, D. Deverell, F. Fox, P. Gronowski, A. Jain, M. Leary, A. Olesin, S. D. Persels, P. Rubinfeld, D. Schumacher, B. Supnik, T. Thrush

引用次数: 10

Abstract

A processor implemented with 180K transistors in 2μm CMOS technology will be presented. The chip size is 9.7mm × 9.4mm, and the instruction set is compatible with a minicomputer.

查看原文本刊更多论文

具有片上指令、数据缓存和内存管理的32b CMOS微处理器

将介绍采用2μm CMOS技术实现180K晶体管的处理器。芯片尺寸为9.7mm × 9.4mm，指令集与小型机兼容。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

自引率

0.00%

发文量