19ns存储器

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1987.1157127

A. Suzuki, S. Yamaguchi, H. Ito, N. Suzuki, T. Yabu

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引用次数: 5

摘要

本文将介绍一种用于高速缓存系统的CMOS存储器，它包括49K位SRAM和约3500个用于逻辑的晶体管。使用地址转换检测，存储器从地址到命中的访问时间为19ns，从标签到命中的访问时间为9.5ns。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 19ns memory

A CMOS memory for cache systems which includes 49K bits SRAM and about 3500 transistors for logic will be presented. The memory achieves access times of 19ns from address to hit and 9.5ns from tag to hit, using address transition detection.

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来源期刊

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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