{"title":"DRAM单元结构与技术","authors":"A. Shah","doi":"10.1109/ISSCC.1987.1157163","DOIUrl":null,"url":null,"abstract":"Over a dozen different cell structures and technologies have been proposed in the past few years to reduce DRAM cell size. Each of the proposals represents a tradeoff between process complexity, cell size and cell perfarmance. This panel will attempt to identify the advantages and disadvantages of these competing approaches and try to understand the trend in cell structures and technologies for the next generation of DRAMs.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"XXX 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"DRAM cell structures and technologies\",\"authors\":\"A. Shah\",\"doi\":\"10.1109/ISSCC.1987.1157163\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Over a dozen different cell structures and technologies have been proposed in the past few years to reduce DRAM cell size. Each of the proposals represents a tradeoff between process complexity, cell size and cell perfarmance. This panel will attempt to identify the advantages and disadvantages of these competing approaches and try to understand the trend in cell structures and technologies for the next generation of DRAMs.\",\"PeriodicalId\":102932,\"journal\":{\"name\":\"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"XXX 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1987.1157163\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1987.1157163","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Over a dozen different cell structures and technologies have been proposed in the past few years to reduce DRAM cell size. Each of the proposals represents a tradeoff between process complexity, cell size and cell perfarmance. This panel will attempt to identify the advantages and disadvantages of these competing approaches and try to understand the trend in cell structures and technologies for the next generation of DRAMs.