50ns DSP并行处理结构

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1987.1157130

K. Kaneko, T. Nakagawa, A. Kiuchi, Y. Hagiwara, H. Ueda, H. Matsushima, T. Akazawa, T. Satoh, J. Ishida

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引用次数: 19

摘要

本报告将介绍一种可编程DSP，它通过两级指令层次结构来避免I/O瓶颈。该IC在149mm2的芯片上包含430K个晶体管。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 50ns DSP with parallel processing architecture

This report will cover a programmable DSP that avoids I/O bottlenecks through a two-level hierarchy of instructions. The IC contains 430K transistors on a 149mm2die.

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来源期刊

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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