M. Okabe, M. Tatsuki, K. Sakaue, T. Hirao, Y. Kuramitsu
{"title":"An ECL gate array hardened against soft errors","authors":"M. Okabe, M. Tatsuki, K. Sakaue, T. Hirao, Y. Kuramitsu","doi":"10.1109/ISSCC.1987.1157091","DOIUrl":null,"url":null,"abstract":"A 1.3μm gate array whose soft error rate is improved by a factor of 100 over a conventional design will be reported.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1987.1157091","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A 1.3μm gate array whose soft error rate is improved by a factor of 100 over a conventional design will be reported.