一个100ns 16点CCD余弦变换处理器

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1987.1157203

A. Chiang, P. Bennett, B. Kosicki, R. Mountain, G. Lincoln, J. Reinold

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引用次数: 7

摘要

本文将介绍一种基于矢量矩阵积算法的CCD，该CCD采用256个定权四象限乘法器实现。在3.3 MHz时钟速率下，已演示了15亿次/秒40dB动态范围和1%精度。芯片尺寸为4平方毫米，功耗为720mW。

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A 100ns 16-point CCD cosine transform processor

A CCD based on the vector matrix product algorithm, that has been implemented using 256 fixed weight four-quadrant multipliers will be described. 1.5 billion operations/s 40dB dynamic range and 1% accuracy have been demonstrated at a 3.3 MHz clock rate. The chip size is 4mm square and it dissipates 720mW.

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来源期刊

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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