{"title":"多芯片计算机扫描路径测试","authors":"R. Schuchard, D. Weiss","doi":"10.1109/ISSCC.1987.1157190","DOIUrl":null,"url":null,"abstract":"On-chip test support circuitry has been developed for a 32b multichip VLSI computer. The test support consists of a test PLA and a 45MHz diagnostic interface port that multiplexes up to 16 serial scan paths. While requiring less than 10% of chip area and power, it supports testing, characterization and diagnosis from chip to system level.","PeriodicalId":102932,"journal":{"name":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Scan path testing of a multichip computer\",\"authors\":\"R. Schuchard, D. Weiss\",\"doi\":\"10.1109/ISSCC.1987.1157190\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"On-chip test support circuitry has been developed for a 32b multichip VLSI computer. The test support consists of a test PLA and a 45MHz diagnostic interface port that multiplexes up to 16 serial scan paths. While requiring less than 10% of chip area and power, it supports testing, characterization and diagnosis from chip to system level.\",\"PeriodicalId\":102932,\"journal\":{\"name\":\"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1987.1157190\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1987.1157190","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On-chip test support circuitry has been developed for a 32b multichip VLSI computer. The test support consists of a test PLA and a 45MHz diagnostic interface port that multiplexes up to 16 serial scan paths. While requiring less than 10% of chip area and power, it supports testing, characterization and diagnosis from chip to system level.