Two CMOS 0.5µm 32b digital macros

A P.41R OF 5-port general-purpose-register file (GPK) and an Arithmetic-Logic-Unit ALU will be reported. Based on a 0 . 5 ~ gate CMOS technology , an access time of 6.5ns in the GPR and an ADD speed of 8.0ns in the ALU have been measured. Sub ns performance reflects feasibility of operating CMOS FET system above 50”l-Iz. The macro circuits were custom-designed with a structured bit-cell approach. The logic function of one bit in different macros such as GPR, ALU and LSSD register, has been optimized within a given bit-width. Mask artwork of the macros is laid out using l p m CMOS ground rules with the exception of sub-micron gate length. Table 1 summarizes some features of the technology which utilizes two levels of metal for wiring and self-aligned Ti-silicide both on diffusion and polysilicon.