A 100ns 16-point CCD cosine transform processor

Abstract

A CCD based on the vector matrix product algorithm, that has been implemented using 256 fixed weight four-quadrant multipliers will be described. 1.5 billion operations/s 40dB dynamic range and 1% accuracy have been demonstrated at a 3.3 MHz clock rate. The chip size is 4mm square and it dissipates 720mW.