4Mb pseudo/virtually SRAM

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1987.1157228

S. Yoshioka, Y. Nagatomo, S. Takahashi, S. Miyamoto, M. Uesugi

引用次数: 11

Abstract

This report will discuss a 512K×8 CMOS RAM with two modes of self-refresh operation, The chip utilizes a dynamic buried stacked capacitor memory cell that attains a 40fF storage capacitance in 16.8μm2. The design has an access time of 95ns with refresh operation and is assembled in a 600-mil 32 pin dual in line package.

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4Mb伪/虚拟SRAM

本报告将讨论具有两种自刷新操作模式的512K×8 CMOS RAM，该芯片采用动态埋置堆叠电容存储单元，在16.8μm2内实现40fF的存储电容。该设计具有95ns的刷新操作访问时间，并在600-mil 32引脚双列封装中组装。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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