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Technical digest. International Electron Devices Meeting最新文献

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High-performance single-crystalline-silicon TFTs on a non-alkali glass substrate 在非碱玻璃基板上的高性能单晶硅tft
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175904
Y. Sano, M. Takei, A. Hara, N. Sasaki
{"title":"High-performance single-crystalline-silicon TFTs on a non-alkali glass substrate","authors":"Y. Sano, M. Takei, A. Hara, N. Sasaki","doi":"10.1109/IEDM.2002.1175904","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175904","url":null,"abstract":"A new single-crystal silicon growth method for fabricating high-performance thin-film transistors (TFTs) was developed. High-performance TFTs - with an 8-/spl mu/m-wide and 20-/spl mu/m-long single-crystal silicon region and a field-effect mobility of 580 cm/sup 2//Vs for the n-channel and 330 cm/sup 2//Vs for the p-channel - were fabricated below 450/spl deg/C on a 300/spl times/300 mm/sup 2/ non-alkali glass substrate.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"24 1","pages":"565-568"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78559888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Electrical integrity of state-of-the-art 0.13 /spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication 电子完整性最先进的0.13 /spl mu/m SOI CMOS器件和电路转移到三维(3D)集成电路(IC)制造
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175992
K. Guarini, Anna W. Topol, M. Ieong, R. Yu, L. Shi, M. Newport, D. Frank, D. V. Singh, G. Cohen, S. Nitta, D. Boyd, P. O'Neil, S. Tempest, H. B. Pogge, S. Purushothaman, W. Haensch
{"title":"Electrical integrity of state-of-the-art 0.13 /spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication","authors":"K. Guarini, Anna W. Topol, M. Ieong, R. Yu, L. Shi, M. Newport, D. Frank, D. V. Singh, G. Cohen, S. Nitta, D. Boyd, P. O'Neil, S. Tempest, H. B. Pogge, S. Purushothaman, W. Haensch","doi":"10.1109/IEDM.2002.1175992","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175992","url":null,"abstract":"We introduce a new scheme for building three-dimensional (3D) integrated circuits (ICs) based on the layer transfer of completed devices. We demonstrate for the first time that the processes required for stacking active device layers preserve the intrinsic electrical characteristics of state-of-the-art short-channel MOSFETs and ring oscillator circuits, which is critical to the success of high performance 3D ICs.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"9 1","pages":"943-945"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73073248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 137
A novel 0.79 /spl mu/m/sup 2/ SRAM cell by KrF lithography and high performance 90 nm CMOS technology for ultra high speed SRAM 采用KrF光刻技术和高性能90纳米CMOS技术，实现了0.79 /spl mu/m/sup 2/超高速SRAM单元
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175868
Soon-Moon Jung, H. Kwon, Jaehun Jeong, W. Cho, Sungbong Kim, H. Lim, K. Koh, Youngseop Rah, Jaekyun Park, Heesoo Kang, G. Lyu, J. Park, C. Chang, Y. Jang, Donggun Park, Kinam Kim, Moon-Yong Lee
{"title":"A novel 0.79 /spl mu/m/sup 2/ SRAM cell by KrF lithography and high performance 90 nm CMOS technology for ultra high speed SRAM","authors":"Soon-Moon Jung, H. Kwon, Jaehun Jeong, W. Cho, Sungbong Kim, H. Lim, K. Koh, Youngseop Rah, Jaekyun Park, Heesoo Kang, G. Lyu, J. Park, C. Chang, Y. Jang, Donggun Park, Kinam Kim, Moon-Yong Lee","doi":"10.1109/IEDM.2002.1175868","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175868","url":null,"abstract":"The smallest SRAM cell, 0.79 /spl mu/m/sup 2/, was realized by a revolutionary cell layout, fine tuned OPC technique to overcome the 248 nm KrF lithography limitation, instead of using 193 nm ArF lithography. Sub-100 nm CMOS technology was indispensable to achieve the cell size as well as the performance. The high performance transistors were made with 80 nm gate length including 15 /spl Aring/ nitrided gate oxide layer, indium channel and halo implantation processes. The novel cell exhibits excellent neutron SER immunity, compared with ones of the SRAM cell by previous generation technologies.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"66 1","pages":"419-422"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74247544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Ultra-thin, high-resolution, flexible electronic ink displays addressed by a-Si active-matrix TFT backplanes on stainless steel foil 超薄，高分辨率，柔性电子墨水显示器由不锈钢箔上的a-Si有源矩阵TFT背板解决
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175860
Y. Chen, J. Au, P. Kazlas, A. Ritenour, H. Gates, J. Goodman
{"title":"Ultra-thin, high-resolution, flexible electronic ink displays addressed by a-Si active-matrix TFT backplanes on stainless steel foil","authors":"Y. Chen, J. Au, P. Kazlas, A. Ritenour, H. Gates, J. Goodman","doi":"10.1109/IEDM.2002.1175860","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175860","url":null,"abstract":"Ultra-thin, flexible displays were fabricated using electronic ink and a-Si TFT backplanes on stainless steel foil substrates. The fabricated TFTs have a linear mobility of 0.5 cm/sup 2//Vs and an ON/OFF ratio of 5/spl times/10/sup 6/. TFT characteristics under bias-temperature-stress and mechanical stress are discussed. These 0.3 mm thick displays have 96 dpi resolution, with 160/spl times/240 pixels on a 3.1\" diagonal active area. Near 180/spl deg/ viewing angle and a contrast ratio of 8.5:1 were achieved.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"60 11","pages":"389-392"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/IEDM.2002.1175860","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72479985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
High-capacitance Cu/Ta2O5/Cu MIM structure for SoC applications featuring a single-mask add-on process 高电容Cu/Ta2O5/Cu MIM结构，用于SoC应用，具有单掩模附加工艺
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175991
T. Ishikawa, D. Kodama, Y. Matsui, M. Hiratani, T. Furusawa, D. Hisamoto
{"title":"High-capacitance Cu/Ta2O5/Cu MIM structure for SoC applications featuring a single-mask add-on process","authors":"T. Ishikawa, D. Kodama, Y. Matsui, M. Hiratani, T. Furusawa, D. Hisamoto","doi":"10.1109/IEDM.2002.1175991","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175991","url":null,"abstract":"This paper presents a metal-insulator-metal capacitor for SoC applications which has the highest capacitance density (up to 12 fF//spl mu/m/sup 2/) ever reported for a device in this field. The simple MIM structure allowed development of the process as a single-mask add-on to conventional Cu BEOL processing.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"33 1","pages":"940-942"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85403364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
Future 1T1C FRAM technologies for highly reliable, high density FRAM 未来1T1C FRAM技术为高可靠性，高密度FRAM
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175900
S.Y. Lee, K. Kim
{"title":"Future 1T1C FRAM technologies for highly reliable, high density FRAM","authors":"S.Y. Lee, K. Kim","doi":"10.1109/IEDM.2002.1175900","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175900","url":null,"abstract":"Recent 32 Mb FRAM technologies realizing 0.25 /spl mu/m/15F2 cell are introduced and key integration technologies for future highly reliable, high density FRAM are suggested. Etchless capacitor technology and MOCVD PZT technology are the promising solutions for realizing future highly reliable, high density FRAM beyond 32 Mb density.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"3 1","pages":"547-550"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81654498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Electronic switching effect in phase-change memory cells 相变存储单元中的电子开关效应
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175987
A. Pirovano, A. Lacaita, D. Merlani, A. Benvenuti, F. Pellizzer, R. Bez
{"title":"Electronic switching effect in phase-change memory cells","authors":"A. Pirovano, A. Lacaita, D. Merlani, A. Benvenuti, F. Pellizzer, R. Bez","doi":"10.1109/IEDM.2002.1175987","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175987","url":null,"abstract":"A detailed investigation of the characteristic current-voltage (I-V) curve and electronic switching effect in chalcogenide-based phase-change memory devices is presented. An original bandgap model of both crystalline and amorphous chalcogenide and a physical picture of the fundamental effects involved in device operation is proposed. The model provides a quantitative description of the device behavior in both DC and transient regime. Finally, simulation results in good agreement with measurements and data reported in literature are presented.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"5 1","pages":"923-926"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84152788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Impact of gate area on plasma charging damage: the "reverse" antenna effect 栅极面积对等离子体充电损伤的影响:“反向”天线效应
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175895
A. Krishnan, S. Krishnan, P. Nicollian
{"title":"Impact of gate area on plasma charging damage: the \"reverse\" antenna effect","authors":"A. Krishnan, S. Krishnan, P. Nicollian","doi":"10.1109/IEDM.2002.1175895","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175895","url":null,"abstract":"We report for the first time, a peak in the failure fraction when plotted as a function of the gate area (for a fixed antenna area). This peak is a consequence of competition between failure probability decrease due to reducing antenna ratio and failure probability increase due to increasing gate area. The position of this peak depends on plasma/oxide parameters, and is likely to be more prevalent in damage arising from high-density plasma processes for ultra-thin dielectrics. The presence of this peak results in a region where the decrease in antenna ratio (by increasing gate area) actually results in higher fail probability (\"reverse\" antenna effect).","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"46 1","pages":"525-528"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84639637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A sub-400/spl deg/C germanium MOSFET technology with high-/spl kappa/ dielectric and metal gate 一个低于400/spl度/C的锗MOSFET技术，具有高/spl kappa/介电和金属栅极
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175872
C. O. Chui, Hyoungsub Kim, D. Chi, B. Triplett, P. McIntyre, K. Saraswat
{"title":"A sub-400/spl deg/C germanium MOSFET technology with high-/spl kappa/ dielectric and metal gate","authors":"C. O. Chui, Hyoungsub Kim, D. Chi, B. Triplett, P. McIntyre, K. Saraswat","doi":"10.1109/IEDM.2002.1175872","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175872","url":null,"abstract":"A novel low thermal budget (/spl les/400/spl deg/C) germanium MOS process with high-/spl kappa/ gate dielectric and metal gate electrode has been demonstrated. For the first time, self-aligned surface-channel Ge p-MOSFETs with ZrO/sub 2/ gate dielectric having equivalent oxide thickness (EOT) of 6-10 /spl Aring/ and platinum gate electrode are demonstrated with twice the low-field hole mobility of Si MOSFETs.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"50 1","pages":"437-440"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85141333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 124
Low field mobility characteristics of sub-100 nm unstrained and strained Si MOSFETs 亚100nm非应变和应变Si mosfet的低场迁移率特性
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175775
K. Rim, S. Narasimha, M. Longstreet, A. Mocuta, J. Cai
{"title":"Low field mobility characteristics of sub-100 nm unstrained and strained Si MOSFETs","authors":"K. Rim, S. Narasimha, M. Longstreet, A. Mocuta, J. Cai","doi":"10.1109/IEDM.2002.1175775","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175775","url":null,"abstract":"A novel mobility extraction technique showed that the mobility enhancements in strained Si MOSFETs were retained in deep sub-100 nm channel lengths. Mobility measurement in devices with channel lengths down to 40 nm was demonstrated by a dR/dL extraction method. The results confirmed and quantified the mobility enhancements despite the presence of high halo doping in scaled strained Si MOSFETs.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"143 1","pages":"43-46"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83996548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 81
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