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Extreme scaling with ultra-thin Si channel MOSFETs 超薄硅沟道mosfet的极限缩放
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175829
Bruce B. Doris, M. Ieong, T. Kanarsky, Ying Zhang, R. Roy, O. Dokumaci, Z. Ren, F. Jamin, L. Shi, W. Natzle, Hsiang-Jen Huang, J. Mezzapelle, A. Mocuta, S. Womack, Michael A. Gribelyuk, E. C. Jones, R. J. Miller, Hon-Sum Philip Wong, Wilfried Haensch
{"title":"Extreme scaling with ultra-thin Si channel MOSFETs","authors":"Bruce B. Doris, M. Ieong, T. Kanarsky, Ying Zhang, R. Roy, O. Dokumaci, Z. Ren, F. Jamin, L. Shi, W. Natzle, Hsiang-Jen Huang, J. Mezzapelle, A. Mocuta, S. Womack, Michael A. Gribelyuk, E. C. Jones, R. J. Miller, Hon-Sum Philip Wong, Wilfried Haensch","doi":"10.1109/IEDM.2002.1175829","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175829","url":null,"abstract":"We examine the scaling limits for planar single gate technology using the ultra-thin Si channel MOSFET. Characteristics for extreme scaled devices with physical gate lengths down to 6 nm and SOI channels as thin as 4 nm are presented. For the first time, we report ring oscillators with 26 nm gate lengths and ultra-thin Si channels.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"1 1","pages":"267-270"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79990457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 191
A new multi-channel dual-gate poly-Si TFT employing excimer laser annealing recrystallization on pre-patterned a-Si thin film 采用准分子激光退火在预图像化A - si薄膜上再结晶的新型多通道双栅多晶硅TFT
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175903
I. Song, C. Kim, S.H. Kang, W. Nam, A.K. Han
{"title":"A new multi-channel dual-gate poly-Si TFT employing excimer laser annealing recrystallization on pre-patterned a-Si thin film","authors":"I. Song, C. Kim, S.H. Kang, W. Nam, A.K. Han","doi":"10.1109/IEDM.2002.1175903","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175903","url":null,"abstract":"We have proposed a new excimer laser annealing method which employs a floating a-Si thin film structure and the effect of pre-patterning. The proposed ELA produces two-dimensional grain growth so that a high quality grain structure can be obtained. We have also fabricated poly-Si TFTs by adapting the proposed ELA method. The dual-gate structure is used for the elimination of grain boundaries in the channel. The proposed poly-Si TFT exhibits high performance electrical characteristics, e.g. a high mobility of 504 cm/sup 2//V sec and low subthreshold slope of 0.337 V/dec.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"17 1","pages":"561-564"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82598545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Improved intermodulation distortion profile of AlGaN/GaN HEMT at high drain bias voltage 高漏偏置电压下AlGaN/GaN HEMT互调畸变谱的改进
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175933
M. Nagahara, T. Kikkawa, N. Adachi, Y. Tateno, S. Kato, M. Yokoyama, S. Yokogawa, T. Kimura, Y. Yamaguchi, N. Hara, K. Joshin
{"title":"Improved intermodulation distortion profile of AlGaN/GaN HEMT at high drain bias voltage","authors":"M. Nagahara, T. Kikkawa, N. Adachi, Y. Tateno, S. Kato, M. Yokoyama, S. Yokogawa, T. Kimura, Y. Yamaguchi, N. Hara, K. Joshin","doi":"10.1109/IEDM.2002.1175933","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175933","url":null,"abstract":"We demonstrate, for the first time, the excellent linearity characteristics of AlGaN/GaN HEMTs at drain bias voltages up to 30 V, class AB operation, at 1.9 GHz. AlGaN/GaN HEMTs with a drain periphery of 1 mm, grown on SiC substrates, exhibit a third-order intermodulation distortion (IM3) of -34.7 dBc for an output power level of 26 dBm, 8 dB back-off from saturation power (Psat), at drain bias voltage of 30 V. Furthermore, we will show the linearity characteristics dependence on Vds and describe that superior linearity profile can be obtained with AlGaN/GaN HEMTs at high drain voltage bias.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"21 1","pages":"693-696"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81760138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A novel silicon Geiger-mode avalanche photodiode 一种新型硅盖革模式雪崩光电二极管
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175958
J. C. Jackson, A. Morrison, D. Phelan, A. Mathewson
{"title":"A novel silicon Geiger-mode avalanche photodiode","authors":"J. C. Jackson, A. Morrison, D. Phelan, A. Mathewson","doi":"10.1109/IEDM.2002.1175958","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175958","url":null,"abstract":"Dark count nonlinearity in CMOS compatible, single photon counting, Geiger-mode avalanche photodiodes (GM-APD) has been investigated. A novel structure was designed, fabricated, and characterized to allow dark count optimization. Dark count levels for the proposed structure are shown to scale linearly with area.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"140 1","pages":"797-800"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76424798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
A novel stack capacitor cell for high density FeRAM compatible with CMOS logic 一种兼容CMOS逻辑的高密度FeRAM堆叠电容器电池
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175899
T. Hayashi, Y. Igarashi, D. Inomata, T. Ichimori, T. Mitsuhashi, K. Ashikaga, T. Ito, M. Yoshimaru, M. Nagata, S. Mitarai, H. Godaiin, T. Nagahama, C. Isobe, H. Moriya, M. Shoji, Y. Ito, H. Kuroda, M. Sasaki
{"title":"A novel stack capacitor cell for high density FeRAM compatible with CMOS logic","authors":"T. Hayashi, Y. Igarashi, D. Inomata, T. Ichimori, T. Mitsuhashi, K. Ashikaga, T. Ito, M. Yoshimaru, M. Nagata, S. Mitarai, H. Godaiin, T. Nagahama, C. Isobe, H. Moriya, M. Shoji, Y. Ito, H. Kuroda, M. Sasaki","doi":"10.1109/IEDM.2002.1175899","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175899","url":null,"abstract":"We have developed 4 Mb 1T1C FeRAM device technology using 0.25 /spl mu/m design rules, which is fully compatible with CMOS logic. This consists of three key technologies: a diffusion barrier and an oxidation barrier to W-plug, low thermal budget process for SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT)-capacitors and no via contact cell scheme.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"15 12 1","pages":"543-546"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86935436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Modeling of ultrahighly doped shallow junctions for aggressively scaled CMOS 大规模缩放CMOS中超高掺杂浅结的建模
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175976
H. Kennel, S. Cea, A. Lilak, P. Keys, M. Giles, J. Hwang, J. Sandford, S. Corcoran
{"title":"Modeling of ultrahighly doped shallow junctions for aggressively scaled CMOS","authors":"H. Kennel, S. Cea, A. Lilak, P. Keys, M. Giles, J. Hwang, J. Sandford, S. Corcoran","doi":"10.1109/IEDM.2002.1175976","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175976","url":null,"abstract":"This paper presents an integrated modeling approach to address diffusion and activation challenges in sub-90 nm CMOS technology. Co-implants of F and Ge are shown to reduce diffusion rates and a new model for the interactive effects is presented. Complex codiffusion behavior of As and P is presented and modeling concepts elucidated. Tradeoffs such as sheet resistance for a given junction depth, and how these depend on impurities, as well as soak vs. spike rapid thermal anneals (RTA), can be understood with simulation models.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"58 1","pages":"875-878"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88362014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Modeling of metal-induced-lateral-crystallization mechanism for optimization of high performance thin-film-transistor fabrication 基于金属诱导横向结晶机制的高性能薄膜晶体管制造优化建模
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175905
C.F. Cheng, M. Poon, C. Kok, M. Chan
{"title":"Modeling of metal-induced-lateral-crystallization mechanism for optimization of high performance thin-film-transistor fabrication","authors":"C.F. Cheng, M. Poon, C. Kok, M. Chan","doi":"10.1109/IEDM.2002.1175905","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175905","url":null,"abstract":"A model to predict metal-induced-lateral-crystallization (MILC) growth rate, polysilicon grain size and metal impurity distribution is proposed. The accuracy of the model has been validated by experimental results obtained from SIMS analysis. It is believed that the model gives important information for superior MILC device fabrication and development.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"54 1","pages":"569-572"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88400109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
15-nm-thick Si channel wall vertical double-gate MOSFET 15nm厚Si沟道壁垂直双栅极MOSFET
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175994
M. Masahara, T. Matsukawa, K. Ishii, Yongxun Liu, H. Tanoue, K. Sakamoto, T. Sekigawa, H. Yamauchi, S. Kanemaru, E. Suzuki
{"title":"15-nm-thick Si channel wall vertical double-gate MOSFET","authors":"M. Masahara, T. Matsukawa, K. Ishii, Yongxun Liu, H. Tanoue, K. Sakamoto, T. Sekigawa, H. Yamauchi, S. Kanemaru, E. Suzuki","doi":"10.1109/IEDM.2002.1175994","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175994","url":null,"abstract":"Double-gate (DG) MOSFET structures have been regarded as promising candidates for scalable CMOS devices. Among DG concept devices, a vertical type has attracted considerable attention due to its process compatibility with conventional CMOS technology and its suitability with bulk Si substrates. The critical issue is fabrication technology, especially for the ultra-thin Si wall for the vertical transistor. This paper demonstrates, for the first time, vertical DG MOSFETs ('IMOSFETs') with a 15-nm-thick channel wall fabricated by using the newly-discovered ion-bombardment-retarded etching (IBRE) of Si in a tetramethylammonium hydroxide (TMAH) solution.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"7 1","pages":"949-951"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89088566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Novel low offset voltage diode using asymmetric threshold voltage MONOS-FET for next generation devices demanding low voltage operation 新型低偏置电压二极管，采用非对称阈值电压单极管场效应晶体管，用于要求低电压工作的下一代器件
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175875
S. Ueno, H. Furuta, Y. Okumura, T. Eimori, Y. Inoue
{"title":"Novel low offset voltage diode using asymmetric threshold voltage MONOS-FET for next generation devices demanding low voltage operation","authors":"S. Ueno, H. Furuta, Y. Okumura, T. Eimori, Y. Inoue","doi":"10.1109/IEDM.2002.1175875","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175875","url":null,"abstract":"Novel diode with low offset voltage below 0.6V is proposed by using MONOS FET with asymmetric threshold voltage. Offset voltage of 0.3V can be achieved by suppressing off state current and reverse leakage current. This technique gives promising characteristics for next generation circuits with low voltage operation.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"55 1","pages":"449-452"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89103818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Novel light emitting device with ultrafast color switching 具有超快颜色切换的新型发光器件
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175788
R. Koudelka, J. Woodall, E. Harmon
{"title":"Novel light emitting device with ultrafast color switching","authors":"R. Koudelka, J. Woodall, E. Harmon","doi":"10.1109/IEDM.2002.1175788","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175788","url":null,"abstract":"A novel light-emitting device capable of ultrafast switching of the output wavelength is proposed and demonstrated. The device achieves an electrical modulation bandwidth in excess of 1.75 GHz at 905 nm. The device contains two light-emitting regions separated by a transition region. Minority electrons are photogenerated in the device using an external CW optical pump. The light emission color is toggled by spatially relocating minority carriers from one light-emitting region (905 run peak wavelength) to another (797 nm peak wavelength) as a result of an applied voltage.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"1 1","pages":"99-102"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88676675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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