一种兼容CMOS逻辑的高密度FeRAM堆叠电容器电池

Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI:10.1109/IEDM.2002.1175899

T. Hayashi, Y. Igarashi, D. Inomata, T. Ichimori, T. Mitsuhashi, K. Ashikaga, T. Ito, M. Yoshimaru, M. Nagata, S. Mitarai, H. Godaiin, T. Nagahama, C. Isobe, H. Moriya, M. Shoji, Y. Ito, H. Kuroda, M. Sasaki

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引用次数: 14

摘要

我们开发了4 Mb 1T1C FeRAM器件技术，采用0.25 /spl mu/m设计规则，完全兼容CMOS逻辑。这包括三个关键技术:w插头的扩散屏障和氧化屏障，SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT)电容器的低热预算工艺和无通孔接触电池方案。

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A novel stack capacitor cell for high density FeRAM compatible with CMOS logic

We have developed 4 Mb 1T1C FeRAM device technology using 0.25 /spl mu/m design rules, which is fully compatible with CMOS logic. This consists of three key technologies: a diffusion barrier and an oxidation barrier to W-plug, low thermal budget process for SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT)-capacitors and no via contact cell scheme.

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来源期刊

Technical digest. International Electron Devices Meeting

CiteScore

4.50

自引率

0.00%

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