T. Hayashi, Y. Igarashi, D. Inomata, T. Ichimori, T. Mitsuhashi, K. Ashikaga, T. Ito, M. Yoshimaru, M. Nagata, S. Mitarai, H. Godaiin, T. Nagahama, C. Isobe, H. Moriya, M. Shoji, Y. Ito, H. Kuroda, M. Sasaki
{"title":"A novel stack capacitor cell for high density FeRAM compatible with CMOS logic","authors":"T. Hayashi, Y. Igarashi, D. Inomata, T. Ichimori, T. Mitsuhashi, K. Ashikaga, T. Ito, M. Yoshimaru, M. Nagata, S. Mitarai, H. Godaiin, T. Nagahama, C. Isobe, H. Moriya, M. Shoji, Y. Ito, H. Kuroda, M. Sasaki","doi":"10.1109/IEDM.2002.1175899","DOIUrl":null,"url":null,"abstract":"We have developed 4 Mb 1T1C FeRAM device technology using 0.25 /spl mu/m design rules, which is fully compatible with CMOS logic. This consists of three key technologies: a diffusion barrier and an oxidation barrier to W-plug, low thermal budget process for SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT)-capacitors and no via contact cell scheme.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"15 12 1","pages":"543-546"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Technical digest. International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2002.1175899","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 14
Abstract
We have developed 4 Mb 1T1C FeRAM device technology using 0.25 /spl mu/m design rules, which is fully compatible with CMOS logic. This consists of three key technologies: a diffusion barrier and an oxidation barrier to W-plug, low thermal budget process for SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT)-capacitors and no via contact cell scheme.
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