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Technical digest. International Electron Devices Meeting最新文献

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FinFET scaling to 10 nm gate length FinFET缩放到10nm栅极长度
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175825
B. Yu, Leland Chang, Shibly S. Ahmed, H. Wang, S. Bell, Chih-Yuh Yang, C. Tabery, C. Ho, Q. Xiang, T. King, J. Bokor, C. Hu, M. Lin, D. Kyser
{"title":"FinFET scaling to 10 nm gate length","authors":"B. Yu, Leland Chang, Shibly S. Ahmed, H. Wang, S. Bell, Chih-Yuh Yang, C. Tabery, C. Ho, Q. Xiang, T. King, J. Bokor, C. Hu, M. Lin, D. Kyser","doi":"10.1109/IEDM.2002.1175825","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175825","url":null,"abstract":"While the selection of new \"backbone\" device structure in the era of post-planar CMOS is open to a few candidates, FinFET and its variants show great potential in scalability and manufacturability for nanoscale CMOS. In this paper we report the design, fabrication, performance, and integration issues of double-gate FinFETs with the physical gate length being aggressively shrunk down to 10 nm and the fin width down to 12 nm. These MOSFETs are believed to be the smallest double-gate transistors ever fabricated. Excellent short-channel performance is observed in devices with a wide range of gate lengths (10/spl sim/105 nm). The observed short-channel behavior outperforms any reported single-gate silicon MOSFETs. Due to the [110] channel crystal orientation, hole mobility in the fabricated p-channel FinFET exceeds greatly that in a traditional planar MOSFET. At 105 nm gate length, the p-channel FinFET shows a record-high transconductance of 633 /spl mu/S//spl mu/m at a V/sub dd/ of 1.2 V. Working CMOS FinFET inverters are also demonstrated.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"03 1","pages":"251-254"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86329794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 580
Saddle add-on metallisation (SAM) for RF inductor implementation in standard IC interconnects 鞍座附加金属化(SAM)用于射频电感器在标准IC互连中的实现
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175880
B. Rejaei, J. Burghartz, H. Schellevis
{"title":"Saddle add-on metallisation (SAM) for RF inductor implementation in standard IC interconnects","authors":"B. Rejaei, J. Burghartz, H. Schellevis","doi":"10.1109/IEDM.2002.1175880","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175880","url":null,"abstract":"A cost-effective add-on process module is proposed for reduction of ohmic losses of RF inductors and interconnects in RF/BiCMOS and RF/CMOS technologies built on logic CMOS processes. The module is based on the local thickening of the top metal layer of the thin CMOS interconnects by Cu plating. A record quality factor of 13 is achieved for a 10-nH inductor on a conventional 5-/spl Omega/-cm silicon substrate.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"89 1","pages":"467-470"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86676089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance 沟槽隔离诱导的机械应力对MOSFET电性能影响的精确建模
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175792
R. Bianchi, G. Bouché, O. Roux‐dit‐Buisson
{"title":"Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance","authors":"R. Bianchi, G. Bouché, O. Roux‐dit‐Buisson","doi":"10.1109/IEDM.2002.1175792","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175792","url":null,"abstract":"A new approach is presented aimed at modeling mechanical stress effects which impact MOSFET electrical behavior. It is successful in accounting for mobility variations experimentally evidenced on complex MOSFET geometries. The newly developed mobility model proves to be an efficient way to include mechanical stress effects into standard simulation models. We show that stress effects can and should be taken into account in the IC design phase in present and sub 90 nm nodes CMOS generations.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"10 1","pages":"117-120"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88110288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 146
A fully integrated Al2O3 trench capacitor DRAM for sub-100 nm technology 一种用于亚100纳米技术的完全集成的Al2O3沟槽电容DRAM
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175968
H. Seidl, M. Gutsche, U. Schroeder, A. Birner, T. Hecht, S. Jakschik, J. Luetzen, M. Kerber, S. Kudelka, T. Popp, A. Orth, H. Reisinger, A. Saenger, K. Schupke, B. Sell
{"title":"A fully integrated Al2O3 trench capacitor DRAM for sub-100 nm technology","authors":"H. Seidl, M. Gutsche, U. Schroeder, A. Birner, T. Hecht, S. Jakschik, J. Luetzen, M. Kerber, S. Kudelka, T. Popp, A. Orth, H. Reisinger, A. Saenger, K. Schupke, B. Sell","doi":"10.1109/IEDM.2002.1175968","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175968","url":null,"abstract":"For the first time, fully integrated 128 Mb trench DRAMs using Al/sub 2/O/sub 3/ as high-k node dielectric in silicon-insulator-silicon (SIS) capacitors were successfully fabricated. A highly manufacturable integration scheme for Al/sub 2/O/sub 3/ as node dielectric in trench capacitors was developed and successfully implemented in a 170 nm ground rule technology. A capacitance close to 50 fF/cell with leakage current well below 1 fA/cell was achieved, leading to significantly improved retention characteristics. 128 Mb DRAM devices with full functionality and excellent test yields were obtained. The scalability of this technology to smaller dimensions is demonstrated by the integration of ALD (Atomic Layer Deposition) Al/sub 2/O/sub 3/ into 110 nm ground rule trench capacitors. In addition, trench capacitors with Al/sub 2/O/sub 3/ on hemispherical grain (HSG) silicon were fabricated, exhibiting high capacitance enhancement with low leakage current.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"33 1","pages":"839-842"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87239304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A broad-band scalable lumped-element inductor model using analytic expressions to incorporate skin effect, substrate loss, and proximity effect 一个宽带可扩展的集总元件电感模型，使用解析表达式来考虑趋肤效应、衬底损耗和邻近效应
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175881
F. Rotella, V. Blaschke, D. Howard
{"title":"A broad-band scalable lumped-element inductor model using analytic expressions to incorporate skin effect, substrate loss, and proximity effect","authors":"F. Rotella, V. Blaschke, D. Howard","doi":"10.1109/IEDM.2002.1175881","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175881","url":null,"abstract":"A new broad-band scalable spiral inductor model incorporating skin effect, substrate loss, and proximity effect is presented. The construction of the lumped element model using analytic expressions is described and the model is validated with data from multiple technologies. Extensions to differential inductors with measured validation is also provided.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"122 1","pages":"471-474"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90270670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Mass-productive ultra-low temperature ALD SiO/sub 2/ process promising for sub-90 nm memory and logic devices 大规模生产的超低温ALD SiO/sub 2/工艺有望用于90纳米以下的存储和逻辑器件
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175819
Jae-Eun Park, J. Ku, Joo-Won Lee, Jong-ho Yang, K. Chu, Seung‐Hwan Lee, M. Park, N. Lee, Ho-Kyu Kang, K. Suh, Byoung-Ha Cho, Byoung-Chul Kim, C. Shin
{"title":"Mass-productive ultra-low temperature ALD SiO/sub 2/ process promising for sub-90 nm memory and logic devices","authors":"Jae-Eun Park, J. Ku, Joo-Won Lee, Jong-ho Yang, K. Chu, Seung‐Hwan Lee, M. Park, N. Lee, Ho-Kyu Kang, K. Suh, Byoung-Ha Cho, Byoung-Chul Kim, C. Shin","doi":"10.1109/IEDM.2002.1175819","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175819","url":null,"abstract":"For the first time, ultra-low temperature ALD SiO/sub 2/ is successfully developed and applied on W/WN/poly-Si stack gates as a dual spacer for the enhancement of data retention time. ALD SiO/sub 2/ deposition is performed at 75/spl deg/C using HCD and H/sub 2/O as precursors and pyridine as a catalyst. Using the ALD SiO/sub 2/ process, SiO/sub 2/ layers are deposited on W/WN/poly-Si stack gates without W oxidation. The gate resistances of the W/WN/poly-Si stack gates do not exhibit any difference between SiN single spacer and SiO/sub 2//SiN dual spacer schemes, which indicates that W oxidation does not occur during the ALD SiO/sub 2/ deposition for dual spacer formation. Conclusively, the significant improvement (>50%) of data retention time is achieved by employing SiO/sub 2//SiN dual spacers at W/WN/poly-Si stack gates in a 130 nm DRAM device. In addition, excellent short channel characteristics of Vth are identified by applying a low temperature ALD SiO/sub 2/ layer as a dual spacer on sub-100 nm SRAM devices.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"1 1","pages":"229-232"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89698633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Short-channel like effects in Schottky barrier carbon nanotube field-effect transistors 肖特基势垒碳纳米管场效应晶体管中的短沟道效应
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175834
J. Appenzeller, J. Knoch, R. Martel, V. Derycke, S. Wind, P. Avouris
{"title":"Short-channel like effects in Schottky barrier carbon nanotube field-effect transistors","authors":"J. Appenzeller, J. Knoch, R. Martel, V. Derycke, S. Wind, P. Avouris","doi":"10.1109/IEDM.2002.1175834","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175834","url":null,"abstract":"This study shows new results on vertically scaled carbon nanotube field-effect transistors (CNFETs) focusing in particular on short-channel effects. We show clear evidence that state-of-the-art CNFETs behave as Schottky barrier (SB) transistors and that SB-CNFETs exhibit a very distinct scaling behavior. The relevant scaling rules that have to be applied to ensure the desired device operation and to avoid short-channel-like effects of CNFETs are discussed for the first time.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"38 1","pages":"285-288"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88863764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
High efficient 820 nm MOS Ge quantum dot photodetectors for short-reach integrated optical receivers with 1300 and 1550 nm sensitivity 用于近程集成光接收器的高效820 nm MOS Ge量子点光电探测器，具有1300和1550 nm的灵敏度
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175786
B. Hsu, S. Chang, C. Shie, C. Lai, P. Chen, C. Liu
{"title":"High efficient 820 nm MOS Ge quantum dot photodetectors for short-reach integrated optical receivers with 1300 and 1550 nm sensitivity","authors":"B. Hsu, S. Chang, C. Shie, C. Lai, P. Chen, C. Liu","doi":"10.1109/IEDM.2002.1175786","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175786","url":null,"abstract":"A metal-oxide-semiconductor (MOS) Ge quantum dot photodetector is demonstrated. The oxide is grown directly on Ge substrate by liquid phase deposition (LPD). The photodetector has the responsivity of 130, 0.16, and 0.08 mA/W under the wavelength of 820 nm, 1300 nm, and 1550 nm, respectively. The dark current is extremely low (0.06 mA/cm/sup 2/). The high performance of Ge quantum dot MOS photodetectors at 820 nm makes it feasible to integrate optoelectronic devices into the Si chip for short-reach optical communication.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"71 1","pages":"91-94"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88478245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Drain-accelerated degradation of tunnel oxides in Flash memories 快闪记忆体中隧道氧化物的漏极加速降解
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175805
A. Chimenton, A. Spinelli, D. Ielmini, A. Lacaita, A. Visconti, P. Olivo
{"title":"Drain-accelerated degradation of tunnel oxides in Flash memories","authors":"A. Chimenton, A. Spinelli, D. Ielmini, A. Lacaita, A. Visconti, P. Olivo","doi":"10.1109/IEDM.2002.1175805","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175805","url":null,"abstract":"A new technique for separating the oxide damage due to program/erase (P/E) cycling and of parasitic hot-hole injection due to bitline biasing in Flash memories is presented. The technique is based on an analysis of the spatial distribution of anomalous tail cells in the array subjected to P/E cycling. We show that electron and hole injection have different dependences on the number of P/E cycles, with the latter becoming the dominating mechanism for large cycling.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"20 1","pages":"167-170"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81321090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Ka-band 2.3W power AlGaN/GaN heterojunction FET
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175929
K. Kasahara, H. Miyamoto, Y. Ando, Y. Okamoto, T. Nakayama, M. Kuzuhara
{"title":"Ka-band 2.3W power AlGaN/GaN heterojunction FET","authors":"K. Kasahara, H. Miyamoto, Y. Ando, Y. Okamoto, T. Nakayama, M. Kuzuhara","doi":"10.1109/IEDM.2002.1175929","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175929","url":null,"abstract":"Describes the first successful watt-level Ka-band power operation of an AlGaN/GaN heterojunction FET fabricated on a SiC substrate. Taking the advantage of high breakdown voltage, high-current, and high-gain characteristics of the short-channel GaN-based FET, state-of-the-art high-power performance of >2W has been achieved at 30GHz from a single chip having a gate width of 0.36mm. The developed device with a gate length of 0.25/spl mu/m exhibited a linear gain of 8.8dB at 30GHz, indicating that the short-channel AlGaN/GaN FET is promising for a variety of high-power applications at Ka-band and above.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"40 1","pages":"677-680"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80106171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
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