{"title":"鞍座附加金属化(SAM)用于射频电感器在标准IC互连中的实现","authors":"B. Rejaei, J. Burghartz, H. Schellevis","doi":"10.1109/IEDM.2002.1175880","DOIUrl":null,"url":null,"abstract":"A cost-effective add-on process module is proposed for reduction of ohmic losses of RF inductors and interconnects in RF/BiCMOS and RF/CMOS technologies built on logic CMOS processes. The module is based on the local thickening of the top metal layer of the thin CMOS interconnects by Cu plating. A record quality factor of 13 is achieved for a 10-nH inductor on a conventional 5-/spl Omega/-cm silicon substrate.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"89 1","pages":"467-470"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Saddle add-on metallisation (SAM) for RF inductor implementation in standard IC interconnects\",\"authors\":\"B. Rejaei, J. Burghartz, H. Schellevis\",\"doi\":\"10.1109/IEDM.2002.1175880\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A cost-effective add-on process module is proposed for reduction of ohmic losses of RF inductors and interconnects in RF/BiCMOS and RF/CMOS technologies built on logic CMOS processes. The module is based on the local thickening of the top metal layer of the thin CMOS interconnects by Cu plating. A record quality factor of 13 is achieved for a 10-nH inductor on a conventional 5-/spl Omega/-cm silicon substrate.\",\"PeriodicalId\":74909,\"journal\":{\"name\":\"Technical digest. International Electron Devices Meeting\",\"volume\":\"89 1\",\"pages\":\"467-470\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-12-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Technical digest. International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2002.1175880\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Technical digest. International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2002.1175880","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Saddle add-on metallisation (SAM) for RF inductor implementation in standard IC interconnects
A cost-effective add-on process module is proposed for reduction of ohmic losses of RF inductors and interconnects in RF/BiCMOS and RF/CMOS technologies built on logic CMOS processes. The module is based on the local thickening of the top metal layer of the thin CMOS interconnects by Cu plating. A record quality factor of 13 is achieved for a 10-nH inductor on a conventional 5-/spl Omega/-cm silicon substrate.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
