C. O. Chui, Hyoungsub Kim, D. Chi, B. Triplett, P. McIntyre, K. Saraswat
{"title":"一个低于400/spl度/C的锗MOSFET技术,具有高/spl kappa/介电和金属栅极","authors":"C. O. Chui, Hyoungsub Kim, D. Chi, B. Triplett, P. McIntyre, K. Saraswat","doi":"10.1109/IEDM.2002.1175872","DOIUrl":null,"url":null,"abstract":"A novel low thermal budget (/spl les/400/spl deg/C) germanium MOS process with high-/spl kappa/ gate dielectric and metal gate electrode has been demonstrated. For the first time, self-aligned surface-channel Ge p-MOSFETs with ZrO/sub 2/ gate dielectric having equivalent oxide thickness (EOT) of 6-10 /spl Aring/ and platinum gate electrode are demonstrated with twice the low-field hole mobility of Si MOSFETs.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"50 1","pages":"437-440"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"124","resultStr":"{\"title\":\"A sub-400/spl deg/C germanium MOSFET technology with high-/spl kappa/ dielectric and metal gate\",\"authors\":\"C. O. Chui, Hyoungsub Kim, D. Chi, B. Triplett, P. McIntyre, K. Saraswat\",\"doi\":\"10.1109/IEDM.2002.1175872\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel low thermal budget (/spl les/400/spl deg/C) germanium MOS process with high-/spl kappa/ gate dielectric and metal gate electrode has been demonstrated. For the first time, self-aligned surface-channel Ge p-MOSFETs with ZrO/sub 2/ gate dielectric having equivalent oxide thickness (EOT) of 6-10 /spl Aring/ and platinum gate electrode are demonstrated with twice the low-field hole mobility of Si MOSFETs.\",\"PeriodicalId\":74909,\"journal\":{\"name\":\"Technical digest. International Electron Devices Meeting\",\"volume\":\"50 1\",\"pages\":\"437-440\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-12-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"124\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Technical digest. International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2002.1175872\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Technical digest. International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2002.1175872","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A sub-400/spl deg/C germanium MOSFET technology with high-/spl kappa/ dielectric and metal gate
A novel low thermal budget (/spl les/400/spl deg/C) germanium MOS process with high-/spl kappa/ gate dielectric and metal gate electrode has been demonstrated. For the first time, self-aligned surface-channel Ge p-MOSFETs with ZrO/sub 2/ gate dielectric having equivalent oxide thickness (EOT) of 6-10 /spl Aring/ and platinum gate electrode are demonstrated with twice the low-field hole mobility of Si MOSFETs.