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Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference最新文献

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L/sup 2/RFM-local layout realistic faults mapping scheme for analogue integrated circuits 模拟集成电路的L/sup 2/ rfm -局部布局实际故障映射方案
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510600
M.J. Ohletz
{"title":"L/sup 2/RFM-local layout realistic faults mapping scheme for analogue integrated circuits","authors":"M.J. Ohletz","doi":"10.1109/CICC.1996.510600","DOIUrl":"https://doi.org/10.1109/CICC.1996.510600","url":null,"abstract":"A new fault modelling scheme for analogue ICs called Local Layout Realistic Fault Mapping is introduced. It is aimed at realistic fault assumptions prior to the final layout. Defects are assumed and their electrical failure modes are evaluated. It turned out that some faults at schematic level are unrealistic, new types of fault emerge and the distribution of faults changes. For a CMOS operational amplifier the number of faults dropped from 45 to 27.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"14 5 1","pages":"475-478"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83556595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Fast and accurate delay estimation for use in timing driven layout for FPGAs with segmented channels 用于分段通道fpga时序驱动布局的快速准确的延迟估计
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510571
S. Kaptanoglu
{"title":"Fast and accurate delay estimation for use in timing driven layout for FPGAs with segmented channels","authors":"S. Kaptanoglu","doi":"10.1109/CICC.1996.510571","DOIUrl":"https://doi.org/10.1109/CICC.1996.510571","url":null,"abstract":"Timing delays for FPGAs with segmented channels can be accurately estimated by most SPICE-like circuit simulators. Such simulators however, are too slow to be of any use inside an iterative automatic timing driven layout (ATDL) engine, which may repeat the computations millions of times. Other methods such as half-perimeter approximation are very easy and fast to compute, but accuracy is very poor for these kinds of FPGAs. The method published by Chew and Lien [1994] overcomes these problems; however, it introduces a very large number of fitted parameters, and its accuracy decreases for more complicated topologies. We present a method similar to Chew and Lien's, but with better accuracy and far fewer coefficients. This is achieved by taking advantage of the symmetry of the problem under the permutation group S/sub N/ of N objects.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"23 1","pages":"341-344"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87339867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A pipelined digital differential matched filter FPGA implementation and VLSI design 一种流水线式数字差分匹配滤波器的FPGA实现和VLSI设计
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510515
Kuang-Chan Liu, Wun-Chang Lin, Chorng-Kuang Wang
{"title":"A pipelined digital differential matched filter FPGA implementation and VLSI design","authors":"Kuang-Chan Liu, Wun-Chang Lin, Chorng-Kuang Wang","doi":"10.1109/CICC.1996.510515","DOIUrl":"https://doi.org/10.1109/CICC.1996.510515","url":null,"abstract":"A digital matched filter having a differential and pipelined structure is proposed for CDMA (Code Division Multiple Access) communication systems. A novel differential PN (Pseudo-Noise) code scheme is adopted to reduce the number of multiplication and summation (M&S). The PDDMF (Pipelined Digital Differential Matched Filter) not only saves half of the hardware and power, but also improves the speed to a single operation time of M&S. These features make the PDDMF more suitable for personal communication high speed and low power requirements than the conventional methods. The FPGA of the DDMF (Digital Differential Matched Filter) verifies the matched filter using the proposed differential PN code scheme. Moreover, a 64 taps length PDDMF with 4 bits soft decision using 5 V 0.8 /spl mu/m CMOS standard cells is designed. The active chip area is 2.6/spl times/2.6 mm/sup 2/. Simulation results demonstrate that the chip rate of the PN code in the PDDMF can achieve 45 M chips/sec.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"47 1","pages":"75-78"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85582489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Standard cell interconnect length prediction from structural circuit attributes 从结构电路属性预测标准单元互连长度
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510535
H. Heineken, Wojciech Maly
{"title":"Standard cell interconnect length prediction from structural circuit attributes","authors":"H. Heineken, Wojciech Maly","doi":"10.1109/CICC.1996.510535","DOIUrl":"https://doi.org/10.1109/CICC.1996.510535","url":null,"abstract":"A new interconnect model is proposed that predicts the distribution parameters of net lengths. The model takes as input a standard cell netlist and provides as output estimates of the mean and variance offer length on a net by net basis. The model was developed and verified on designs produced with two different place and route algorithms.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"34 1","pages":"167-170"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73087510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A 1.8 V 36 mW DSP for the half-rate speech codec 一个1.8 V 36mw的DSP用于半速率语音编解码器
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510578
T. Shiraishi, K. Kawamoto, K. Ishikawa, H. Sato, F. Asai, E. Teraoka, T. Kengaku, H. Takata, T. Tokuda, K. Nishida, K. Saitoh
{"title":"A 1.8 V 36 mW DSP for the half-rate speech codec","authors":"T. Shiraishi, K. Kawamoto, K. Ishikawa, H. Sato, F. Asai, E. Teraoka, T. Kengaku, H. Takata, T. Tokuda, K. Nishida, K. Saitoh","doi":"10.1109/CICC.1996.510578","DOIUrl":"https://doi.org/10.1109/CICC.1996.510578","url":null,"abstract":"A low-power 16-bit DSP has been developed to realize a low bit-rate speech codec. A dual datapath architecture and low-power circuit design techniques are employed to reduce power consumption. The PDC half-rate speech codec is implemented in the DSP with 36 mW at 1.8 V.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"205 1","pages":"371-374"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77004961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A very high performance and manufacturable 3.3 V 0.35-/spl mu/m CMOS technology for ASICs 一种非常高性能和可制造的3.3 V 0.35-/spl mu/m的asic CMOS技术
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510506
I. Kizilyalli, S. Lytle, B. Jones, E. Martin, S.F. Shive, A.L. Brooks, M. Thoma, R.W. Schanzer, J. Sniegowski, D.M. Wroge, R. W. Key, J. Kearney, K.R. Stiles
{"title":"A very high performance and manufacturable 3.3 V 0.35-/spl mu/m CMOS technology for ASICs","authors":"I. Kizilyalli, S. Lytle, B. Jones, E. Martin, S.F. Shive, A.L. Brooks, M. Thoma, R.W. Schanzer, J. Sniegowski, D.M. Wroge, R. W. Key, J. Kearney, K.R. Stiles","doi":"10.1109/CICC.1996.510506","DOIUrl":"https://doi.org/10.1109/CICC.1996.510506","url":null,"abstract":"In this paper a manufacturable and high performance 0.35 /spl mu/m CMOS ASIC technology optimized for 3.3 V operation is presented. This CMOS technology features a 65 /spl Aring/ gate oxide, single n/sup +/-polysilicon gate, and 3 levels of metal. An improvement of 1.6X in circuit performance and 1.56X in packing density is achieved over AT&T's previous generation 0.5 /spl mu/m 3.3 volt CMOS technology by device scaling, and aggressive isolation and interconnect design rules. The nominal ring oscillator delay time is 50 ps.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"10 1","pages":"31-34"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77341392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
SUBWAVE: a methodology for modeling digital substrate noise injection in mixed-signal ICs SUBWAVE:混合信号集成电路中数字衬底噪声注入建模方法
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510581
Paolo Miliozzi, L. Carloni, E. Charbon, A. Sangiovanni-Vincentelli
{"title":"SUBWAVE: a methodology for modeling digital substrate noise injection in mixed-signal ICs","authors":"Paolo Miliozzi, L. Carloni, E. Charbon, A. Sangiovanni-Vincentelli","doi":"10.1109/CICC.1996.510581","DOIUrl":"https://doi.org/10.1109/CICC.1996.510581","url":null,"abstract":"A methodology is presented for generating compact models of substrate noise injection in complex logic networks. For a given gate library, the injection patterns associated with a gate and an input transition scheme are accurately evaluated using device-level simulation. Assuming spatial independence of all noise generating devices, the cumulative switching noise resulting from all injection patterns is efficiently computed using a gate-level event-driven simulator. The resulting injected signal is then sampled and translated into an energy spectrum which accounts for fundamental frequencies as well as glitch energy. Preliminary results demonstrate the validity of the assumptions and the accuracy of the approach on a set of standard benchmark circuits.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"326 1","pages":"385-388"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76134483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 51
A DSP for DCT-based and wavelet-based video codecs for consumer applications 用于消费者应用的基于dct和基于小波的视频编解码器的DSP
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510575
K. Okamoto, Takuya Jinbo, T. Araki, Y. Iizuka, H. Nakajima, M. Takahata, Hisashi Inoue, S. Kurohmaru, T. Yonezawa, K. Aono
{"title":"A DSP for DCT-based and wavelet-based video codecs for consumer applications","authors":"K. Okamoto, Takuya Jinbo, T. Araki, Y. Iizuka, H. Nakajima, M. Takahata, Hisashi Inoue, S. Kurohmaru, T. Yonezawa, K. Aono","doi":"10.1109/CICC.1996.510575","DOIUrl":"https://doi.org/10.1109/CICC.1996.510575","url":null,"abstract":"We have developed a video DSP which performs real-time encoding and decoding for DCT-based algorithms, such as ITU-T H.261, and wavelet-based subband encoding algorithms. This LSI is suitable for consumer applications as it was implemented using 0.5 /spl mu/m-CMOS process technology to realize compactness (1 million transistors on 65 mm/sup 2/) and low power(560 mW). It features a processing unit which performs wavelet filtering at high speeds, a compact DCT circuit, and a fast, flexible DRAM interface for low-cost systems. At 40 MHz, a single chip is capable of processing QCIF size pictures at a rate of over 15 frames/second.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"21 1","pages":"359-362"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/CICC.1996.510575","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72535372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A high-speed low-power 0.3 /spl mu/m CMOS gate array with variable threshold voltage (VT) scheme 一种具有可变阈值电压(VT)方案的高速低功耗0.3 /spl mu/m CMOS门阵列
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510510
T. Kuroda, T. Fujita, T. Nagamatu, S. Yoshioka, T. Sei, K. Matsuo, Y. Hamura, T. Mori, M. Murota, M. Kakumu, T. Sakurai
{"title":"A high-speed low-power 0.3 /spl mu/m CMOS gate array with variable threshold voltage (VT) scheme","authors":"T. Kuroda, T. Fujita, T. Nagamatu, S. Yoshioka, T. Sei, K. Matsuo, Y. Hamura, T. Mori, M. Murota, M. Kakumu, T. Sakurai","doi":"10.1109/CICC.1996.510510","DOIUrl":"https://doi.org/10.1109/CICC.1996.510510","url":null,"abstract":"Circuit techniques for dynamically varying threshold voltage are introduced to reduce active power dissipation by 50% with negligible overhead in speed, standby power and chip area. No additional external power supply or additional step in process is required. A gate array with this scheme is fabricated in a 0.3 /spl mu/m CMOS technology whose performance is investigated. The gate array is best fit for multimedia portable applications that require low standby power dissipation and high performance.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"1 1","pages":"53-56"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76053705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
A 1 GHz CMOS upconversion mixer 1 GHz CMOS上变频混频器
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510542
P. Kinget, M. Steyaert
{"title":"A 1 GHz CMOS upconversion mixer","authors":"P. Kinget, M. Steyaert","doi":"10.1109/CICC.1996.510542","DOIUrl":"https://doi.org/10.1109/CICC.1996.510542","url":null,"abstract":"A high frequency mixer topology is presented for the realization of a 1 GHz upconversion mixer in a standard 0.7 /spl mu/m CMOS technology. The high output bandwidth is achieved by the development of an nMOS only current amplifier to convert the modulated current of an nMOS transistor in the linear region to an output voltage.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"238 1","pages":"197-200"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77618332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 65
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