K. Okamoto, Takuya Jinbo, T. Araki, Y. Iizuka, H. Nakajima, M. Takahata, Hisashi Inoue, S. Kurohmaru, T. Yonezawa, K. Aono
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引用次数: 21
Abstract
We have developed a video DSP which performs real-time encoding and decoding for DCT-based algorithms, such as ITU-T H.261, and wavelet-based subband encoding algorithms. This LSI is suitable for consumer applications as it was implemented using 0.5 /spl mu/m-CMOS process technology to realize compactness (1 million transistors on 65 mm/sup 2/) and low power(560 mW). It features a processing unit which performs wavelet filtering at high speeds, a compact DCT circuit, and a fast, flexible DRAM interface for low-cost systems. At 40 MHz, a single chip is capable of processing QCIF size pictures at a rate of over 15 frames/second.