Fast and accurate delay estimation for use in timing driven layout for FPGAs with segmented channels

Abstract

Timing delays for FPGAs with segmented channels can be accurately estimated by most SPICE-like circuit simulators. Such simulators however, are too slow to be of any use inside an iterative automatic timing driven layout (ATDL) engine, which may repeat the computations millions of times. Other methods such as half-perimeter approximation are very easy and fast to compute, but accuracy is very poor for these kinds of FPGAs. The method published by Chew and Lien [1994] overcomes these problems; however, it introduces a very large number of fitted parameters, and its accuracy decreases for more complicated topologies. We present a method similar to Chew and Lien's, but with better accuracy and far fewer coefficients. This is achieved by taking advantage of the symmetry of the problem under the permutation group S/sub N/ of N objects.