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Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference最新文献

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A new rip-up and reroute algorithm for very large scale gate arrays 超大规模门阵列的一种新的撕裂和重路由算法
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510536
H. Shirota, S. Shibatani, M. Terai
{"title":"A new rip-up and reroute algorithm for very large scale gate arrays","authors":"H. Shirota, S. Shibatani, M. Terai","doi":"10.1109/CICC.1996.510536","DOIUrl":"https://doi.org/10.1109/CICC.1996.510536","url":null,"abstract":"A fast rip-up and reroute algorithm for large scale gate arrays is reported. The algorithm combines 'global' and 'local' rip-up and reroute processes to efficiently eliminate the unconnects introduced by an initial routing process. The global process reduces the local wire congestion by ripping up and rerouting global paths. The local process eliminates the unconnects, mainly caused by routing order dependency, by ripping up and rerouting local paths. The effectiveness of our method is demonstrated by our experimental results on industrial sea-of-gates (SOG) circuits and a well-known benchmark circuit.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"2 1","pages":"171-174"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88271994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A complex array multiplier using distributed arithmetic 使用分布式算法的复杂数组乘法器
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510514
S. He, M. Torkelson
{"title":"A complex array multiplier using distributed arithmetic","authors":"S. He, M. Torkelson","doi":"10.1109/CICC.1996.510514","DOIUrl":"https://doi.org/10.1109/CICC.1996.510514","url":null,"abstract":"The design of an efficient array architecture for the multiplication of complex numbers applying distributed arithmetic is presented. The complex multiplier takes an area just over that of two real multipliers and its speed is almost the same as a single real multiplier. The texture of the design is obtained by an in-depth examination of a real multiplier structure with data in the off-set binary representation. Residue error compensation and the functional requirement of various boundary cells, such as negative weight addition, are discussed in detail. VHDL module with generic parameters has been written and successfully simulated, which enable the complex multiplier module to be included in large designs with required word-lengths for both operands. A test chip has been implemented with a standard library in 0.8 /spl mu/m CMOS process and fabricated.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"11 1 1","pages":"71-74"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85469120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A BiCMOS programmable continuous-time filter using voltage-companding 采用压扩的BiCMOS可编程连续时间滤波器
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510519
G. van Ruymbeke, C. Enz, F. Krummenacher, M. Declercq
{"title":"A BiCMOS programmable continuous-time filter using voltage-companding","authors":"G. van Ruymbeke, C. Enz, F. Krummenacher, M. Declercq","doi":"10.1109/CICC.1996.510519","DOIUrl":"https://doi.org/10.1109/CICC.1996.510519","url":null,"abstract":"This paper presents a BiCMOS realization of a programmable continuous-time filter demonstrating the feasibility of the voltage companding technique. The circuit implements four low-pass filters (order 2,3,4,5) and one band-pass filter (order 2) by interconnecting a set of identical non-linear cells. The filter is obtained by a proper component substitution transforming a g/sub m/-C structure into its log-domain equivalent. The g/sub m/-C structures are derived from LC ladder prototypes which are synthesized using the image-parameter method. The programmable filters can additionally be frequency tuned from 10 kHz to 100 kHz with a very low THD despite their class AB operation (1% for a modulation index of 3 corresponding to an input current of 30 /spl mu/A).","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"98 1","pages":"93-96"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86082989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A mixed-signal decision-feedback equalizer that uses parallelism 一种使用并行性的混合信号决策反馈均衡器
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510503
R. Kajley, J.E.C. Brown, P. Hurst
{"title":"A mixed-signal decision-feedback equalizer that uses parallelism","authors":"R. Kajley, J.E.C. Brown, P. Hurst","doi":"10.1109/CICC.1996.510503","DOIUrl":"https://doi.org/10.1109/CICC.1996.510503","url":null,"abstract":"A mixed-signal decision-feedback equalizer (DFE) that uses parallelism is described. The parallelism in the look-ahead DFE achieves an increase in the data rate over that of a conventional DFE. The DFE occupies 23 mm/sup 2/ in a 2-/spl mu/m CMOS process, operates at 55 Mb/s and dissipates 450 mW.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"73 1","pages":"17-20"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86247463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An intracorporal telemetry for strain gage transducer 应变计传感器体内遥测技术
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510562
J. Bégueret, R. Benbrahim, Zhiqun Li, F. Rodes, J.P. Dom
{"title":"An intracorporal telemetry for strain gage transducer","authors":"J. Bégueret, R. Benbrahim, Zhiqun Li, F. Rodes, J.P. Dom","doi":"10.1109/CICC.1996.510562","DOIUrl":"https://doi.org/10.1109/CICC.1996.510562","url":null,"abstract":"A new strain gage bridge to PPM (Pulse Position Modulation) converter has been developed. It consists of a chopper amplifier and a voltage to time converter associated in a feed-back loop. This topology exhibits mainly an automatic offset cancellation capability, a ratiometric transfer function and an accuracy of 10 bits. Therefore, this converter is insensitive to offset drifts, and is well suited for long term monitoring of orthopedic implants.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"19 1","pages":"295-298"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75107551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Over an order of magnitude DRAM test time reduction by charge offset 通过电荷偏移减少一个数量级以上的DRAM测试时间
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510602
M. Hashimoto, I. Uchida, S. Hatakoshi
{"title":"Over an order of magnitude DRAM test time reduction by charge offset","authors":"M. Hashimoto, I. Uchida, S. Hatakoshi","doi":"10.1109/CICC.1996.510602","DOIUrl":"https://doi.org/10.1109/CICC.1996.510602","url":null,"abstract":"A circuit technique of reducing DRAM data retention test time by over an order of magnitude is described. The circuit requires almost zero area overhead. Data retention test time reduction is achieved by using a charge offset realized by manipulating a dummy cell reference voltage. The retention time parallel shift in logarithmic time domain with respect to charge offset was confirmed experimentally. Overall DRAM test time can be reduced by 2/3 since this amount of time is being utilized to perform the data retention test.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"43 1","pages":"483-486"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87112621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Receiver characterization using periodic small-signal analysis 使用周期性小信号分析的接收机特性
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510594
R. Telichevesky, K. Kundert, J. White
{"title":"Receiver characterization using periodic small-signal analysis","authors":"R. Telichevesky, K. Kundert, J. White","doi":"10.1109/CICC.1996.510594","DOIUrl":"https://doi.org/10.1109/CICC.1996.510594","url":null,"abstract":"Periodic small-signal analysis is a recently developed approach for AC and noise analysis of linear periodically-varying circuits. This paper presents several new approaches to characterizing the transfer functions, noise, and distortion of communication circuits using this new technique. A receiver is used as an example, but the techniques presented are applicable to a wide variety of circuits, including mixers, samplers, sample-and-holds, chopper-stabilized amplifiers, multipliers and switched-capacitor filters.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"12 1","pages":"449-452"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87163597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
An SRAM-based FPGA architecture 基于sram的FPGA架构
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510551
S. Gould, B. Worth, K. Clinton, E. Millham, F. Keyser, R. Palmer, S. Hartman, T. Zittritsch
{"title":"An SRAM-based FPGA architecture","authors":"S. Gould, B. Worth, K. Clinton, E. Millham, F. Keyser, R. Palmer, S. Hartman, T. Zittritsch","doi":"10.1109/CICC.1996.510551","DOIUrl":"https://doi.org/10.1109/CICC.1996.510551","url":null,"abstract":"An SRAM-based FPGA architecture has been developed using a licensed AT6000 architecture base. The logic-cell architecture exploits an efficient, medium-grained, fixed library cell that implements most frequently used synthesis functions. An internal routing structure enables dense designs using a highly connected grid-based routing system and a dedicated I/O routing structure that supports the highest I/O counts available. Dynamic reconfiguration is retained with an underlying SRAM structure like the AT6000.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"13 1","pages":"243-246"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85912457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Structured design of a 288-tap FIR filter by optimized partial product tree compression 基于优化部分积树压缩的288分接FIR滤波器结构设计
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510516
Jun Rim Choi, Lak Hyun Jang, Seong Wook Jung, Jin Ho Choi
{"title":"Structured design of a 288-tap FIR filter by optimized partial product tree compression","authors":"Jun Rim Choi, Lak Hyun Jang, Seong Wook Jung, Jin Ho Choi","doi":"10.1109/CICC.1996.510516","DOIUrl":"https://doi.org/10.1109/CICC.1996.510516","url":null,"abstract":"A compact 10-bit, 288-tap FIR filter is designed by adopting structured architecture which employs optimized partial product tree compression method. The new architecture is based on the addition of equally weighted partial products which result from 288 multiplications of the filter coefficients and the inputs. The 288 multiplication and 287 addition operations are decomposed to add 1440 partial products to meet the tight timing requirement. Optimized parallel compression schemes such as 4:2 and 5:5:2 compressors are used to perform decomposed partial product addition. The completed 288-tap FIR filter occupies 7/spl times/9 mm/sup 2/ of silicon area which consists of 385754 transistors in 0.6 /spl mu/m triple-metal CMOS technology.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"31 1","pages":"79-82"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85144575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
IDDQ testing in low power supply CMOS circuits 低功耗CMOS电路中的IDDQ测试
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510598
C. Tong, M. Wen, S. Su
{"title":"IDDQ testing in low power supply CMOS circuits","authors":"C. Tong, M. Wen, S. Su","doi":"10.1109/CICC.1996.510598","DOIUrl":"https://doi.org/10.1109/CICC.1996.510598","url":null,"abstract":"The I/sub DDQ/ current testing for low power circuits is investigated. Two examples of low power circuits are considered. One involves strictly a decrease in supply voltage, the other reduces supply voltage simultaneously with a scaling down of transistor parameters. Based on the theoretical and simulation results, the gap between faulty I/sub DDQ/ and fault-free I/sub DDQ/ can be seen to decrease in low power supply circuits. For I/sub DDQ/ testing to be effective, the gap should be discriminative. A method of partitioning is provided to solve this problem.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"88 1","pages":"467-470"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81417842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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