IDDQ testing in low power supply CMOS circuits

Abstract

The I/sub DDQ/ current testing for low power circuits is investigated. Two examples of low power circuits are considered. One involves strictly a decrease in supply voltage, the other reduces supply voltage simultaneously with a scaling down of transistor parameters. Based on the theoretical and simulation results, the gap between faulty I/sub DDQ/ and fault-free I/sub DDQ/ can be seen to decrease in low power supply circuits. For I/sub DDQ/ testing to be effective, the gap should be discriminative. A method of partitioning is provided to solve this problem.