Structured design of a 288-tap FIR filter by optimized partial product tree compression

Abstract

A compact 10-bit, 288-tap FIR filter is designed by adopting structured architecture which employs optimized partial product tree compression method. The new architecture is based on the addition of equally weighted partial products which result from 288 multiplications of the filter coefficients and the inputs. The 288 multiplication and 287 addition operations are decomposed to add 1440 partial products to meet the tight timing requirement. Optimized parallel compression schemes such as 4:2 and 5:5:2 compressors are used to perform decomposed partial product addition. The completed 288-tap FIR filter occupies 7/spl times/9 mm/sup 2/ of silicon area which consists of 385754 transistors in 0.6 /spl mu/m triple-metal CMOS technology.