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Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference最新文献

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Exploring multiplier architecture and layout for low power 探索低功耗乘法器架构和布局
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510609
P. Meier, Rob A. Rutenbar, L. R. Carley
{"title":"Exploring multiplier architecture and layout for low power","authors":"P. Meier, Rob A. Rutenbar, L. R. Carley","doi":"10.1109/CICC.1996.510609","DOIUrl":"https://doi.org/10.1109/CICC.1996.510609","url":null,"abstract":"Multiplication represents a fundamental building block in all DSP tasks. Due to the large latency inherent in multiplication, schemes have been devised to minimize the delay. Two methods are common in current implementations: regular arrays and Wallace trees. Previous gate-level analyses have suggested that not only are Wallace trees faster than array schemes, they also consume much less power. However these analyses did not take wiring into account, resulting in optimistic timing and power estimates. We develop a simplified comparative layout methodology to analyze the effect of physical layout on these designs. Results for short bit-width (8, 16, 24 bit) DSP multipliers show that while wiring has a major impact on signal delay and power, Wallace trees still show roughly a 10% power advantage over array-based designs.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"16 1","pages":"513-516"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91326427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 72
Efficiently embedding expertise in high-density process-portable standard cell generators 有效地将专业知识嵌入高密度过程便携式标准细胞发生器中
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510605
J. Duh, T. G. Matheson, E. L. Hepler
{"title":"Efficiently embedding expertise in high-density process-portable standard cell generators","authors":"J. Duh, T. G. Matheson, E. L. Hepler","doi":"10.1109/CICC.1996.510605","DOIUrl":"https://doi.org/10.1109/CICC.1996.510605","url":null,"abstract":"A new approach to the creation of process-portable standard cell generators is described. The system efficiently captures designer expertise while automating the details of the cell layout process. The system takes advantage of the extensibility of the underlying symbolic layout system to provide process portability without sacrificing layout density. The system includes novel transistor-bending and mask-processing automation.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"7 1","pages":"497-500"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88796757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An 8-bit 50+ Msamples/s pipelined A/D converter with an area and power efficient architecture 一个8位50+ Msamples/s的流水线A/D转换器，具有面积和功率效率高的架构
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510589
K. Nagaraj, H. S. Fetterman, R.S. Shariatdoust, J. Anidjar, S. Lewis, J. Alsayegh, R.G. Renninger
{"title":"An 8-bit 50+ Msamples/s pipelined A/D converter with an area and power efficient architecture","authors":"K. Nagaraj, H. S. Fetterman, R.S. Shariatdoust, J. Anidjar, S. Lewis, J. Alsayegh, R.G. Renninger","doi":"10.1109/CICC.1996.510589","DOIUrl":"https://doi.org/10.1109/CICC.1996.510589","url":null,"abstract":"An efficient architecture for a pipelined A/D converter is described. By sharing amplifiers along the pipeline and also completely eliminating the amplifier from the last stage, an 8-bit converter is realized using just 3 amplifiers (instead of 7 amplifiers with a conventional pipeline architecture). By using two such pipelines in parallel, a sampling rate of over 50 Msamples/s has been achieved in a 0.9-/spl mu/m CMOS technology.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"48 2 1","pages":"423-426"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88840155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An FPGA for multi-chip reconfigurable logic 用于多芯片可重构逻辑的FPGA
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510529
R. Amerson, R. Carter, W. Culbertson, P. Kuekes, G. Snider, L. Albertson
{"title":"An FPGA for multi-chip reconfigurable logic","authors":"R. Amerson, R. Carter, W. Culbertson, P. Kuekes, G. Snider, L. Albertson","doi":"10.1109/CICC.1996.510529","DOIUrl":"https://doi.org/10.1109/CICC.1996.510529","url":null,"abstract":"The Plasma chip, designed specifically to address issues important to custom computing machines (CCM), completes a 100% fully automatic place and route in approximately three seconds. Plasma FPGAs using 0.8 micron CMOS are packaged in large multichip modules (MCMs). Plasma introduces some innovative architecture concepts including hardware support for large multiported register files.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"13 1","pages":"137-143"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83630525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers 在同步开关CMOS输出缓冲器中形成阻尼LRC寄生电路
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510558
T. Gabara, W. Fischer, J. Harrington, W. Troutman
{"title":"Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers","authors":"T. Gabara, W. Fischer, J. Harrington, W. Troutman","doi":"10.1109/CICC.1996.510558","DOIUrl":"https://doi.org/10.1109/CICC.1996.510558","url":null,"abstract":"Measurements of a 0.5 /spl mu/m CMOS testchip using several techniques have demonstrated a reduction in the generation of ground bounce. These techniques are: an automatic transistor sizing method that compensates for process, temperature, and supply voltage variations; a self-adjusting internal capacitive load that counteracts the increased switching rate of faster parts; and an integrated resistive element inserted directly into the power and ground leads that dampens the RLC oscillations. Comparison measurements between a conventional buffer and the new buffer have demonstrated that the amplitude and duration of the generated ground bounce has been reduced 2.5/spl times/ and 2/spl times/, respectively. A single external resistor is required to set a reference current.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"46 1","pages":"277-280"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82641989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 60
Efficient frequency domain analysis of large nonlinear analog circuits 大型非线性模拟电路的有效频域分析
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510597
P. Feldmann, B. Melville, D. Long
{"title":"Efficient frequency domain analysis of large nonlinear analog circuits","authors":"P. Feldmann, B. Melville, D. Long","doi":"10.1109/CICC.1996.510597","DOIUrl":"https://doi.org/10.1109/CICC.1996.510597","url":null,"abstract":"In this paper, we present a new implementation of the harmonic balance method which extends its applicability to circuits 2-3 orders of magnitude larger than was previously practical. The results reported here extend our previous work which only considered large circuits operating in a mildly nonlinear regime. The new implementation is based on quadratically convergent Newton methods and is able to simulate general nonlinear circuits. The significant efficiency improvement is achieved by use of Krylov subspace methods and a problem-specific preconditioner for inverting the harmonic balance Jacobian matrix. The analysis of radio-frequency mixers, implemented in integrated circuit technology, is an important application of our new method. We describe the theory behind the method, then report performance results on a complete receiver design using detailed transistor models.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"42 1","pages":"461-464"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79555587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 95
Memory/logic interconnect flexibility in FPGAs with large embedded memory arrays 具有大型嵌入式存储器阵列的fpga中的存储器/逻辑互连灵活性
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510530
S. Wilton, Jonathan Rose, Z. G. Vrancsic
{"title":"Memory/logic interconnect flexibility in FPGAs with large embedded memory arrays","authors":"S. Wilton, Jonathan Rose, Z. G. Vrancsic","doi":"10.1109/CICC.1996.510530","DOIUrl":"https://doi.org/10.1109/CICC.1996.510530","url":null,"abstract":"As the capacities of field-programmable gate arrays (FPGAs) grow, it becomes desirable to create FPGAs with embedded memory arrays. This paper examines the flexibility of the interconnect structure that joins memory and logic. For architectures with only a few memory arrays, we find that both the routability and the delay of circuits are insensitive to the memory/logic interconnect flexibility, which implies that this interconnection can be made very inflexible. This is in contrast to the logic connection block flexibility, which has been shown to require high flexibility. For architectures with more arrays, the memory/logic interconnect flexibility requirements increase and approach those of logic interconnect.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"17 1","pages":"144-147"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90979925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A high density embedded array programmable logic architecture 一种高密度嵌入式阵列可编程逻辑结构
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510553
S. Reddy, R. Cliff, D. Jefferson, C. Lane, C. Sung, B. Wang, J. Huang, Wanli Chang, T. Cope, C. McClintock, W. Leong, B. Ahanin, J. Turner
{"title":"A high density embedded array programmable logic architecture","authors":"S. Reddy, R. Cliff, D. Jefferson, C. Lane, C. Sung, B. Wang, J. Huang, Wanli Chang, T. Cope, C. McClintock, W. Leong, B. Ahanin, J. Turner","doi":"10.1109/CICC.1996.510553","DOIUrl":"https://doi.org/10.1109/CICC.1996.510553","url":null,"abstract":"An SRAM based embedded array programmable logic architecture with densities ranging from 10000 to 100000 gates is discussed in this paper. An embedded array is incorporated into this architecture to implement megafunctions like microprocessors, FIFOs and multipliers efficiently. A multidimensional interconnect scheme is featured to achieve flexible routing between logic blocks, the embedded array and I/O pins. The first member of the family is currently available with a gate density of 50000 gates.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"81 1","pages":"251-254"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84283210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Forward power annotation on physical layout floor-plan 物理布局平面图上的正向功率标注
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510582
R. Zafalon, C. Guardiani, M.C. Rossi, R. Rambaldi
{"title":"Forward power annotation on physical layout floor-plan","authors":"R. Zafalon, C. Guardiani, M.C. Rossi, R. Rambaldi","doi":"10.1109/CICC.1996.510582","DOIUrl":"https://doi.org/10.1109/CICC.1996.510582","url":null,"abstract":"A design methodology that provides the information about the distribution of power on the physical layout is presented in this paper. Unlike previous work, this information can be used to detect possible power distribution problems early in the design cycle. The methodology consists in creating the required links between a gate-level, probabilistic power estimation tool and a floor-planner. In this way the power consumption data can be properly localized with respect to the regioning generated on the physical layout before the actual detailed placement and routing occurs. The application of this technique to the design of a low-power IDCT circuit on a 0.5 /spl mu/m sea-of-gate CMOS technology is presented in this paper, showing the considerable advantages of the proposed method.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"34 1","pages":"389-392"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83673823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 2.5 GHz monolithic silicon image reject filter 一个2.5 GHz单片硅图像抑制滤波器
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510541
J. Macedo, M. Copeland, P. Schvan
{"title":"A 2.5 GHz monolithic silicon image reject filter","authors":"J. Macedo, M. Copeland, P. Schvan","doi":"10.1109/CICC.1996.510541","DOIUrl":"https://doi.org/10.1109/CICC.1996.510541","url":null,"abstract":"A low power 2.5 GHz monolithic silicon bipolar image rejection filter for superheterodyne receiver application is presented; which uses an on-chip inductor and a negative resistance circuit to realize a notch filter with better than 50 dB rejection (measured) at the image frequency. Using 0.8 micron BiCMOS technology a tuned amplifier was fabricated with 1.9 GHz passband, a deep notch at 2.5 GHz to attenuate the image frequency (assuming 300 MHz intermediate frequency (IF)), and 3.2 mA current consumption at +3 V. A second chip incorporated a varactor to add notch frequency tuning capability over a 239 MHz range.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"53 1","pages":"193-196"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79186937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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