Forward power annotation on physical layout floor-plan

A design methodology that provides the information about the distribution of power on the physical layout is presented in this paper. Unlike previous work, this information can be used to detect possible power distribution problems early in the design cycle. The methodology consists in creating the required links between a gate-level, probabilistic power estimation tool and a floor-planner. In this way the power consumption data can be properly localized with respect to the regioning generated on the physical layout before the actual detailed placement and routing occurs. The application of this technique to the design of a low-power IDCT circuit on a 0.5 /spl mu/m sea-of-gate CMOS technology is presented in this paper, showing the considerable advantages of the proposed method.