一个8位50+ Msamples/s的流水线A/D转换器，具有面积和功率效率高的架构

Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI:10.1109/CICC.1996.510589

K. Nagaraj, H. S. Fetterman, R.S. Shariatdoust, J. Anidjar, S. Lewis, J. Alsayegh, R.G. Renninger

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引用次数: 7

摘要

介绍了一种高效的流水线a /D转换器结构。通过沿着管道共享放大器，并且完全消除了最后一级的放大器，仅使用3个放大器就实现了8位转换器(而不是使用传统管道架构的7个放大器)。通过并行使用两个这样的管道，在0.9-/spl mu/m的CMOS技术中实现了超过50 Msamples/s的采样率。

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An 8-bit 50+ Msamples/s pipelined A/D converter with an area and power efficient architecture

An efficient architecture for a pipelined A/D converter is described. By sharing amplifiers along the pipeline and also completely eliminating the amplifier from the last stage, an 8-bit converter is realized using just 3 amplifiers (instead of 7 amplifiers with a conventional pipeline architecture). By using two such pipelines in parallel, a sampling rate of over 50 Msamples/s has been achieved in a 0.9-/spl mu/m CMOS technology.

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来源期刊

Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference

CiteScore

3.80

自引率

0.00%

发文量