A high density embedded array programmable logic architecture

Abstract

An SRAM based embedded array programmable logic architecture with densities ranging from 10000 to 100000 gates is discussed in this paper. An embedded array is incorporated into this architecture to implement megafunctions like microprocessors, FIFOs and multipliers efficiently. A multidimensional interconnect scheme is featured to achieve flexible routing between logic blocks, the embedded array and I/O pins. The first member of the family is currently available with a gate density of 50000 gates.