一种高密度嵌入式阵列可编程逻辑结构

Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI:10.1109/CICC.1996.510553

S. Reddy, R. Cliff, D. Jefferson, C. Lane, C. Sung, B. Wang, J. Huang, Wanli Chang, T. Cope, C. McClintock, W. Leong, B. Ahanin, J. Turner

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引用次数: 6

摘要

本文讨论了一种基于SRAM的密度为10000 ~ 100000门的嵌入式阵列可编程逻辑结构。嵌入式阵列被整合到该架构中，以有效地实现微处理器，fifo和乘法器等大型功能。采用多维互连方案实现逻辑块、嵌入式阵列和I/O引脚之间的灵活路由。该家族的第一个成员目前可用的门密度为50000门。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A high density embedded array programmable logic architecture

An SRAM based embedded array programmable logic architecture with densities ranging from 10000 to 100000 gates is discussed in this paper. An embedded array is incorporated into this architecture to implement megafunctions like microprocessors, FIFOs and multipliers efficiently. A multidimensional interconnect scheme is featured to achieve flexible routing between logic blocks, the embedded array and I/O pins. The first member of the family is currently available with a gate density of 50000 gates.

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来源期刊

Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference

CiteScore

3.80

自引率

0.00%

发文量