通过电荷偏移减少一个数量级以上的DRAM测试时间

Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI:10.1109/CICC.1996.510602

M. Hashimoto, I. Uchida, S. Hatakoshi

{"title":"通过电荷偏移减少一个数量级以上的DRAM测试时间","authors":"M. Hashimoto, I. Uchida, S. Hatakoshi","doi":"10.1109/CICC.1996.510602","DOIUrl":null,"url":null,"abstract":"A circuit technique of reducing DRAM data retention test time by over an order of magnitude is described. The circuit requires almost zero area overhead. Data retention test time reduction is achieved by using a charge offset realized by manipulating a dummy cell reference voltage. The retention time parallel shift in logarithmic time domain with respect to charge offset was confirmed experimentally. Overall DRAM test time can be reduced by 2/3 since this amount of time is being utilized to perform the data retention test.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"43 1","pages":"483-486"},"PeriodicalIF":0.0000,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Over an order of magnitude DRAM test time reduction by charge offset\",\"authors\":\"M. Hashimoto, I. Uchida, S. Hatakoshi\",\"doi\":\"10.1109/CICC.1996.510602\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A circuit technique of reducing DRAM data retention test time by over an order of magnitude is described. The circuit requires almost zero area overhead. Data retention test time reduction is achieved by using a charge offset realized by manipulating a dummy cell reference voltage. The retention time parallel shift in logarithmic time domain with respect to charge offset was confirmed experimentally. Overall DRAM test time can be reduced by 2/3 since this amount of time is being utilized to perform the data retention test.\",\"PeriodicalId\":74515,\"journal\":{\"name\":\"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference\",\"volume\":\"43 1\",\"pages\":\"483-486\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-05-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1996.510602\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1996.510602","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

描述了一种将DRAM数据保留测试时间减少一个数量级以上的电路技术。该电路几乎需要零面积开销。数据保留测试时间的减少是通过使用通过操纵虚拟电池参考电压实现的电荷偏移来实现的。实验证实了保留时间在对数时域内相对于电荷偏移量的平行位移。总的DRAM测试时间可以减少2/3，因为这部分时间被用于执行数据保留测试。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Over an order of magnitude DRAM test time reduction by charge offset

A circuit technique of reducing DRAM data retention test time by over an order of magnitude is described. The circuit requires almost zero area overhead. Data retention test time reduction is achieved by using a charge offset realized by manipulating a dummy cell reference voltage. The retention time parallel shift in logarithmic time domain with respect to charge offset was confirmed experimentally. Overall DRAM test time can be reduced by 2/3 since this amount of time is being utilized to perform the data retention test.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference

CiteScore

3.80

自引率

0.00%

发文量