A high-speed low-power 0.3 /spl mu/m CMOS gate array with variable threshold voltage (VT) scheme

Abstract

Circuit techniques for dynamically varying threshold voltage are introduced to reduce active power dissipation by 50% with negligible overhead in speed, standby power and chip area. No additional external power supply or additional step in process is required. A gate array with this scheme is fabricated in a 0.3 /spl mu/m CMOS technology whose performance is investigated. The gate array is best fit for multimedia portable applications that require low standby power dissipation and high performance.