{"title":"模拟集成电路的L/sup 2/ rfm -局部布局实际故障映射方案","authors":"M.J. Ohletz","doi":"10.1109/CICC.1996.510600","DOIUrl":null,"url":null,"abstract":"A new fault modelling scheme for analogue ICs called Local Layout Realistic Fault Mapping is introduced. It is aimed at realistic fault assumptions prior to the final layout. Defects are assumed and their electrical failure modes are evaluated. It turned out that some faults at schematic level are unrealistic, new types of fault emerge and the distribution of faults changes. For a CMOS operational amplifier the number of faults dropped from 45 to 27.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"14 5 1","pages":"475-478"},"PeriodicalIF":0.0000,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"L/sup 2/RFM-local layout realistic faults mapping scheme for analogue integrated circuits\",\"authors\":\"M.J. Ohletz\",\"doi\":\"10.1109/CICC.1996.510600\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new fault modelling scheme for analogue ICs called Local Layout Realistic Fault Mapping is introduced. It is aimed at realistic fault assumptions prior to the final layout. Defects are assumed and their electrical failure modes are evaluated. It turned out that some faults at schematic level are unrealistic, new types of fault emerge and the distribution of faults changes. For a CMOS operational amplifier the number of faults dropped from 45 to 27.\",\"PeriodicalId\":74515,\"journal\":{\"name\":\"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference\",\"volume\":\"14 5 1\",\"pages\":\"475-478\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-05-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1996.510600\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1996.510600","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new fault modelling scheme for analogue ICs called Local Layout Realistic Fault Mapping is introduced. It is aimed at realistic fault assumptions prior to the final layout. Defects are assumed and their electrical failure modes are evaluated. It turned out that some faults at schematic level are unrealistic, new types of fault emerge and the distribution of faults changes. For a CMOS operational amplifier the number of faults dropped from 45 to 27.