A very high performance and manufacturable 3.3 V 0.35-/spl mu/m CMOS technology for ASICs

Abstract

In this paper a manufacturable and high performance 0.35 /spl mu/m CMOS ASIC technology optimized for 3.3 V operation is presented. This CMOS technology features a 65 /spl Aring/ gate oxide, single n/sup +/-polysilicon gate, and 3 levels of metal. An improvement of 1.6X in circuit performance and 1.56X in packing density is achieved over AT&T's previous generation 0.5 /spl mu/m 3.3 volt CMOS technology by device scaling, and aggressive isolation and interconnect design rules. The nominal ring oscillator delay time is 50 ps.