A 1.8 V 36 mW DSP for the half-rate speech codec

Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI:10.1109/CICC.1996.510578

T. Shiraishi, K. Kawamoto, K. Ishikawa, H. Sato, F. Asai, E. Teraoka, T. Kengaku, H. Takata, T. Tokuda, K. Nishida, K. Saitoh

引用次数: 9

Abstract

A low-power 16-bit DSP has been developed to realize a low bit-rate speech codec. A dual datapath architecture and low-power circuit design techniques are employed to reduce power consumption. The PDC half-rate speech codec is implemented in the DSP with 36 mW at 1.8 V.

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一个1.8 V 36mw的DSP用于半速率语音编解码器

为实现低比特率语音编解码器，研制了一种低功耗16位DSP。采用双数据通路结构和低功耗电路设计技术来降低功耗。PDC半速率语音编解码器在DSP中实现，功率为36mw，电压为1.8 V。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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