一种非常高性能和可制造的3.3 V 0.35-/spl mu/m的asic CMOS技术

Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI:10.1109/CICC.1996.510506

I. Kizilyalli, S. Lytle, B. Jones, E. Martin, S.F. Shive, A.L. Brooks, M. Thoma, R.W. Schanzer, J. Sniegowski, D.M. Wroge, R. W. Key, J. Kearney, K.R. Stiles

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引用次数: 9

摘要

本文提出了一种适合3.3 V工作的、可制造的高性能0.35 /spl μ m CMOS ASIC技术。这种CMOS技术具有65 /spl的Aring/栅极氧化物，单n/sup +/-多晶硅栅极和3级金属。通过器件缩放以及积极的隔离和互连设计规则，与AT&T上一代0.5 /spl mu/m 3.3伏CMOS技术相比，电路性能提高1.6倍，封装密度提高1.56倍。环形振荡器的标称延迟时间为50ps。

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A very high performance and manufacturable 3.3 V 0.35-/spl mu/m CMOS technology for ASICs

In this paper a manufacturable and high performance 0.35 /spl mu/m CMOS ASIC technology optimized for 3.3 V operation is presented. This CMOS technology features a 65 /spl Aring/ gate oxide, single n/sup +/-polysilicon gate, and 3 levels of metal. An improvement of 1.6X in circuit performance and 1.56X in packing density is achieved over AT&T's previous generation 0.5 /spl mu/m 3.3 volt CMOS technology by device scaling, and aggressive isolation and interconnect design rules. The nominal ring oscillator delay time is 50 ps.

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来源期刊

Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference

CiteScore

3.80

自引率

0.00%

发文量