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Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference最新文献

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A highly linear CMOS Gm-C bandpass filter for video applications 用于视频应用的高线性CMOS Gm-C带通滤波器
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510518
Z. Chang, D. Haspeslagh, J. Boxho, D. Macq
{"title":"A highly linear CMOS Gm-C bandpass filter for video applications","authors":"Z. Chang, D. Haspeslagh, J. Boxho, D. Macq","doi":"10.1109/CICC.1996.510518","DOIUrl":"https://doi.org/10.1109/CICC.1996.510518","url":null,"abstract":"A 14th order CMOS transconductance-C (Gm-C) bandpass filter for video applications is described. By using highly linear Gm-C integrators, the filter achieves 75 dB dynamic range over 700 kHz noise bandwidth. The measured IM3 @ 600 kHz is -61 dB for a 4 Vpp input signal. On-chip automatic frequency tuning provides more than 300% center frequency range of the filter with 1% frequency accuracy. The 0.7 /spl mu/m CMOS filter measures 4.8 mm/sup 2/ and consumes 70 mW from a single 5 V power supply.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"39 1","pages":"89-92"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83558016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A 35 Gbit/s throughput 64 kbit CMOS buffer SRAM 35 Gbit/s吞吐量64 kbit CMOS缓冲SRAM
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510555
J. Alowersson, P. Andersson
{"title":"A 35 Gbit/s throughput 64 kbit CMOS buffer SRAM","authors":"J. Alowersson, P. Andersson","doi":"10.1109/CICC.1996.510555","DOIUrl":"https://doi.org/10.1109/CICC.1996.510555","url":null,"abstract":"A 64 kbit 0.8-/spl mu/m pure CMOS buffer memory with 256 bit word-length and 3.6 ns cycle time, allowing 35 Gbit/s throughput, is presented. The memory consumes 1.5 W at the maximum frequency. The short cycle time is achieved through the use of a synchronously pipelined address decoder with one internal level of latches. The address decoder, based on TSPC latches, is described in detail.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"98 1","pages":"261-264"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80805718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Gate-array library design using local interconnect 采用本地互连的门阵列库设计
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510608
L. Wissel, D. Stout, Nathan C. Buck
{"title":"Gate-array library design using local interconnect","authors":"L. Wissel, D. Stout, Nathan C. Buck","doi":"10.1109/CICC.1996.510608","DOIUrl":"https://doi.org/10.1109/CICC.1996.510608","url":null,"abstract":"An ASIC gate-array library has been created in 0.4 /spl mu/m CMOS technology using a local interconnect level. The gate-array cells in this library are denser than their counterparts in a library without local interconnect. The comparison of two benchmarks, including a 520K-gate ASIC routed with both libraries, further shows that the local interconnect allows higher density of ASIC designs due to more efficient use of the global inter-connect layers.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"40 1","pages":"509-512"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84102693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
1.8 GHz tunable filter in Si technology 1.8 GHz可调谐滤波器的硅技术
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510540
S. Pipilos, Y. Tsividis, J. Fenk
{"title":"1.8 GHz tunable filter in Si technology","authors":"S. Pipilos, Y. Tsividis, J. Fenk","doi":"10.1109/CICC.1996.510540","DOIUrl":"https://doi.org/10.1109/CICC.1996.510540","url":null,"abstract":"An active filter using integrated inductors has been implemented in Si bipolar technology. The filter has a second-order bandpass response, with quality factor tunable through Q enhancement and center frequency tunable through reactance multiplication. For a nominal center frequency of 1.8 GHz and a quality factor of 35, the filter has a 1 dB compression dynamic range of 40 dB, and draws 8 mA from a 3 V supply.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"205 1","pages":"189-192"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80351592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Optimal design of op amps for oversampled converters 过采样转换器运算放大器的优化设计
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510570
Feng Wang, R. Harjani
{"title":"Optimal design of op amps for oversampled converters","authors":"Feng Wang, R. Harjani","doi":"10.1109/CICC.1996.510570","DOIUrl":"https://doi.org/10.1109/CICC.1996.510570","url":null,"abstract":"The power consumption for various op amps used in /spl Sigma//spl Delta/ modulators is considered. We first classify the different op amp topologies used in such modulators. We then develop a generalized integrator model that allows us to compare the power consumption for all these topologies. We also derive an expression for the minimum theoretical bound on the power dissipation. We illustrate our results with two design examples: a class A and a class AB op amp. It is shown that class A op amps are the best choice for /spl Sigma//spl Delta/ modulators.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"36 1","pages":"337-340"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90545373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
VLSI implementation of hierarchical motion estimator for MPEG2 MP@HL MPEG2分层运动估计器的VLSI实现MP@HL
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510573
T. Onoye, G. Fujita, I. Shirakawa, K. Matsumura, H. Ariyoshi, S. Tsukiyama
{"title":"VLSI implementation of hierarchical motion estimator for MPEG2 MP@HL","authors":"T. Onoye, G. Fujita, I. Shirakawa, K. Matsumura, H. Ariyoshi, S. Tsukiyama","doi":"10.1109/CICC.1996.510573","DOIUrl":"https://doi.org/10.1109/CICC.1996.510573","url":null,"abstract":"A VLSI motion estimator dedicated to MPEG2 MP@HL has been developed. Adopting a two-level hierarchical searching algorithm in detecting motion vectors, the computational labor can be reduced by 1/70 in comparison with the conventional algorithm. The proposed motion estimator is integrated in a 0.6 /spl mu/m triple-metal CMOS chip which contains 1,200 K transistors on a 12.2/spl times/12.7 mm/sup 2/ die. The input clock rate can be attained up to 133 MHz, which enables the real time motion estimation for MPEG2 MP@HL.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"46 1","pages":"351-354"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86848119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2.7 V CMOS single chip baseband processor for CT2/CT2+ cordless telephones 用于CT2/CT2+无绳电话的2.7 V CMOS单片基带处理器
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510526
C. Crippa, G. Nicollini, P. Confalonieri, S. Pernici, A. Mecchia, P. Rizzo, F. Adduci, E. Viani, I. Bietti, A. Nagari, C. Dallavalle, A. Leblond, P. Busserolle
{"title":"A 2.7 V CMOS single chip baseband processor for CT2/CT2+ cordless telephones","authors":"C. Crippa, G. Nicollini, P. Confalonieri, S. Pernici, A. Mecchia, P. Rizzo, F. Adduci, E. Viani, I. Bietti, A. Nagari, C. Dallavalle, A. Leblond, P. Busserolle","doi":"10.1109/CICC.1996.510526","DOIUrl":"https://doi.org/10.1109/CICC.1996.510526","url":null,"abstract":"A low voltage, low power CMOS single chip baseband processor for CT2 and CT2+ cordless telephones is presented. The chip integrates a complete voiceband codec, a tone generator, a G721 AD-PCM coder/decoder, a Burst Mode Logic controller for CT2/CT2+ framings, and an I/Q baseband signal generator. It can be easily interfaced with standard microcontrollers through a parallel interface. It can operate from a 2.7 V minimum supply with operative and stand-by power consumptions of 35 mW and 25 /spl mu/W, respectively. Maximum operative supply is 5.5 V. Chip area is 55.5 mm/sup 2/ in a 0.8 /spl mu/ N-well CMOS process.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"10 1","pages":"123-126"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89206931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Capacitive coupling and quantized feedback applied to conventional CMOS technology 电容耦合和量化反馈应用于传统CMOS技术
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510559
T. Gabara, W. Fischer
{"title":"Capacitive coupling and quantized feedback applied to conventional CMOS technology","authors":"T. Gabara, W. Fischer","doi":"10.1109/CICC.1996.510559","DOIUrl":"https://doi.org/10.1109/CICC.1996.510559","url":null,"abstract":"An on-chip capacitor which is formed under a bonding pad is used to block the DC level of an external input signal. Quantized feedback using a self-triggered decision circuit is used to establish local DC voltage levels in the receiver and eliminate the \"zero wander\" effect. Measurement of a 0.5 /spl mu/m CMOS chip has demonstrated that: a BER (Bit Error Rate) test for a 2/sup 31/-1 sequence showed no errors at 600 Mb/s; the circuit detected a low frequency signal of 1 Kb/s indicating that coding is not required; and the input signal can be DC biased anywhere, limited only by the ESD diodes, between VDD and VSS without affecting the final recovered CMOS waveform.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"29 1","pages":"281-284"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89681248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
Exploring the power dimension [in digital CMOS] 探索功率尺寸[在数字CMOS中]
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510546
J. Rabaey
{"title":"Exploring the power dimension [in digital CMOS]","authors":"J. Rabaey","doi":"10.1109/CICC.1996.510546","DOIUrl":"https://doi.org/10.1109/CICC.1996.510546","url":null,"abstract":"Keeping the power dissipation within bounds is rapidly becoming one of the main challenges in contemporary digital design. Design experience and research in the early 1990s has amply demonstrated that doing so requires a \"power conscious\" design methodology that addresses dissipation at every level of the design hierarchy. Evidently, this cannot be achieved if no accompanying design automation environment is available. Spurred by this observation, we have seen an intensive effort in the domain of design automation for low power in recent years that has resulted in both academic and industrial tool environments. In this tutorial, we only focus on the analysis facet of the low power design process. Not only is the availability of analysis, simulation, and prediction tools the \"conditio sine qua non\" for low power design, it also represents the most understood and established component of the low-power design methodology. The paper starts with a discussion of power analysis at the circuit and logic design abstraction levels. This domain is becoming relatively mature with multiple entries commercially available. In our opinion, it is the high-level power prediction however that will have the most impact on the reduction of power dissipation. We have therefore included an in-depth discussion on the efforts and results in the so-called \"power exploration\" domain, that includes power prediction and analysis at the RTL level and above.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"33 1","pages":"215-220"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89782604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
High-speed/high-band width design methodologies for on chip DRAM core multimedia system LSIs 片上DRAM核心多媒体系统lsi的高速/高带宽设计方法
Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI: 10.1109/CICC.1996.510556
T. Tsuruda, I. Kobayashi, M. Tsukude, T. Yamagata, K. Arimoto
{"title":"High-speed/high-band width design methodologies for on chip DRAM core multimedia system LSIs","authors":"T. Tsuruda, I. Kobayashi, M. Tsukude, T. Yamagata, K. Arimoto","doi":"10.1109/CICC.1996.510556","DOIUrl":"https://doi.org/10.1109/CICC.1996.510556","url":null,"abstract":"Recently, as multimedia LSIs have developed, the demand for high-speed/high-band width LSIs which integrate the DRAM core and logic elements (CPU etc.) have been strongly required. However, the high-speed/high-band width operation induces the large switching noise. This noise degrades a DRAMs operating margin, and especially the data retention characteristics. In this paper, we analyze the noise transmission model and propose a DRAM and logic compatible design methodology to maintain the reliability of high-speed/high-band width system LSIs. Good experimental results are obtained on the test device.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"15 1","pages":"265-268"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85395463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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