Gate-array library design using local interconnect

An ASIC gate-array library has been created in 0.4 /spl mu/m CMOS technology using a local interconnect level. The gate-array cells in this library are denser than their counterparts in a library without local interconnect. The comparison of two benchmarks, including a 520K-gate ASIC routed with both libraries, further shows that the local interconnect allows higher density of ASIC designs due to more efficient use of the global inter-connect layers.