VLSI implementation of hierarchical motion estimator for MPEG2 MP@HL

Abstract

A VLSI motion estimator dedicated to MPEG2 MP@HL has been developed. Adopting a two-level hierarchical searching algorithm in detecting motion vectors, the computational labor can be reduced by 1/70 in comparison with the conventional algorithm. The proposed motion estimator is integrated in a 0.6 /spl mu/m triple-metal CMOS chip which contains 1,200 K transistors on a 12.2/spl times/12.7 mm/sup 2/ die. The input clock rate can be attained up to 133 MHz, which enables the real time motion estimation for MPEG2 MP@HL.