35 Gbit/s吞吐量64 kbit CMOS缓冲SRAM

Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI:10.1109/CICC.1996.510555

J. Alowersson, P. Andersson

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引用次数: 4

摘要

提出了一种64 kbit的0.8-/spl mu/m纯CMOS缓冲存储器，具有256位字长和3.6 ns周期时间，吞吐量为35 Gbit/s。最高频率时内存消耗1.5 W。短周期时间是通过使用具有一个内部锁存器级别的同步流水线地址解码器实现的。详细介绍了基于TSPC锁存器的地址解码器。

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A 35 Gbit/s throughput 64 kbit CMOS buffer SRAM

A 64 kbit 0.8-/spl mu/m pure CMOS buffer memory with 256 bit word-length and 3.6 ns cycle time, allowing 35 Gbit/s throughput, is presented. The memory consumes 1.5 W at the maximum frequency. The short cycle time is achieved through the use of a synchronously pipelined address decoder with one internal level of latches. The address decoder, based on TSPC latches, is described in detail.

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来源期刊

Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference

CiteScore

3.80

自引率

0.00%

发文量