A 35 Gbit/s throughput 64 kbit CMOS buffer SRAM

Abstract

A 64 kbit 0.8-/spl mu/m pure CMOS buffer memory with 256 bit word-length and 3.6 ns cycle time, allowing 35 Gbit/s throughput, is presented. The memory consumes 1.5 W at the maximum frequency. The short cycle time is achieved through the use of a synchronously pipelined address decoder with one internal level of latches. The address decoder, based on TSPC latches, is described in detail.