High-speed/high-band width design methodologies for on chip DRAM core multimedia system LSIs

Abstract

Recently, as multimedia LSIs have developed, the demand for high-speed/high-band width LSIs which integrate the DRAM core and logic elements (CPU etc.) have been strongly required. However, the high-speed/high-band width operation induces the large switching noise. This noise degrades a DRAMs operating margin, and especially the data retention characteristics. In this paper, we analyze the noise transmission model and propose a DRAM and logic compatible design methodology to maintain the reliability of high-speed/high-band width system LSIs. Good experimental results are obtained on the test device.