2021 IEEE International Interconnect Technology Conference (IITC)最新文献_第9页

Localization length of integrated multi-walled carbon nanotubes 集成多壁碳纳米管的定位长度

2021 IEEE International Interconnect Technology Conference (IITC) Pub Date : 2014-05-20 DOI: 10.1109/IITC.2014.6831852

H. Fiedler, S. Hermann, M. Rennau, S. Schulz, T. Gessner

引用次数: 0

Reliability of segmented edge seal ring for RF devices 射频器件分段边缘密封圈的可靠性

2021 IEEE International Interconnect Technology Conference (IITC) Pub Date : 2014-05-20 DOI: 10.1109/IITC.2014.6831836

J. Gambino, R. Graf, J. Malinowski, A. Cote, W. Guthrie, K. Watson, P. Chapman, K. K. Sims, M. D. Levy, T. Aoki, G. A. Mason, M. Jaffe

引用次数: 3

Through-silicon-via material property variation impact on full-chip reliability and timing 通硅通孔材料性能变化对全芯片可靠性和时序的影响

2021 IEEE International Interconnect Technology Conference (IITC) Pub Date : 2014-05-20 DOI: 10.1109/IITC.2014.6831846

Moongon Jung, D. Pan, S. Lim

引用次数: 5

Advanced metal and dielectric barrier cap films for Cu low k interconnects 用于Cu低k互连的先进金属和介质阻挡帽膜

2021 IEEE International Interconnect Technology Conference (IITC) Pub Date : 2014-05-20 DOI: 10.1109/IITC.2014.6831866

D. Priyadarshini, S. Nguyen, H. Shobha, S. Cohen, T. Shaw, E. Liniger, C. K. Hu, C. Parks, E. Adams, J. Burnham, A. Simon, G. Bonilla, A. Grill, D. Canaperi, D. Edelstein, D. Collins, M. Balseanu, M. Stolfi, J. Ren, K. Shah

{"title":"Advanced metal and dielectric barrier cap films for Cu low k interconnects","authors":"D. Priyadarshini, S. Nguyen, H. Shobha, S. Cohen, T. Shaw, E. Liniger, C. K. Hu, C. Parks, E. Adams, J. Burnham, A. Simon, G. Bonilla, A. Grill, D. Canaperi, D. Edelstein, D. Collins, M. Balseanu, M. Stolfi, J. Ren, K. Shah","doi":"10.1109/IITC.2014.6831866","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831866","url":null,"abstract":"Multi-layer SiN barrier film with high breakdown and low leakage is developed for Cu low k interconnects and is compared with the SiCNH barrier film used at previous technology nodes. Ultra-thin SiN barrier cap film also provides high conformality and fills recess in Cu lines observed post CMP. A significant enhancement in electro migration (EM) performance was obtained by selectively depositing Co on top of Cu lines followed by conformal multi-layer SiN barrier film. Further EM lifetime improvement is obtained by using a Co liner to form a wrap around structure with completely encapsulated Cu. An integrated in-situ preclean/ metal/dielectric cap chamber was used to avoid any oxidation of Cu/Co layers. Kinetic studies of CVD Co liner/Co cap samples show significant increase in EM activation energy (1.7 eV) over samples with dielectric only barrier film (0.9-1 eV). The complete wrap around structure with Co liner and Co cap shows improved device reliability.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"14 1","pages":"185-188"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84368741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Impact of die partitioning on reliability and yield of 3D DRAM 晶片分割对3D DRAM可靠性及良率的影响

2021 IEEE International Interconnect Technology Conference (IITC) Pub Date : 2014-05-20 DOI: 10.1109/IITC.2014.6831841

Woongrae Kim, Daehyun Kim, Hee Il Hong, L. Milor, S. Lim

引用次数: 3

3D sequential integration opportunities and technology optimization 3D顺序集成机会和技术优化

2021 IEEE International Interconnect Technology Conference (IITC) Pub Date : 2014-05-20 DOI: 10.1109/IITC.2014.6831837

P. Batude, B. Sklénard, C. Fenouillet-Béranger, B. Previtali, C. Tabone, O. Rozeau, O. Billoint, O. Turkyilmaz, H. Sarhan, S. Thuries, G. Cibrario, L. Brunet, F. Deprat, J.-E Michallet, F. Clermidy, M. Vinet

引用次数: 43

Restoration and pore sealing of low-k films by UV-assisted processes 紫外光辅助工艺对低钾薄膜的修复和孔隙密封

2021 IEEE International Interconnect Technology Conference (IITC) Pub Date : 2014-05-20 DOI: 10.1109/IITC.2014.6831901

Bo Xie, Kelvin Chan, D. Cui, He Ren, Daemian Raj, E. Hollar, Sanjeev Baluja, J. Rocha, M. Naik, A. Demos

{"title":"Restoration and pore sealing of low-k films by UV-assisted processes","authors":"Bo Xie, Kelvin Chan, D. Cui, He Ren, Daemian Raj, E. Hollar, Sanjeev Baluja, J. Rocha, M. Naik, A. Demos","doi":"10.1109/IITC.2014.6831901","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831901","url":null,"abstract":"Porous low-k dielectrics are susceptible to damages by steps such as etch, ash, and CMP in the BEOL process flow. Such damages degrade the structural and electrical properties of low-k materials. To uphold the value of integrating low-k dielectrics, restoration processes are needed to repair such damages. In this work, UV-assisted silylation is used to repair damages and restore properties of porous low-k dielectrics. The repair process is able to restore carbon content, as indicated by the increase in water contact angle (WCA), and restore the electrical properties, as shown by the decrease in dielectric constant (k) and increase in break-down electrical field based on blanket-film data. On structured wafers, the post-etch repair process effects a 4-6% reduction in RC when compared to without repair. The same UV-assisted platform may be used to effect pore sealing to prevent metals used in BEOL metallization from penetrating into porous low-k materials. On structured wafers, the pore-sealing process is able to reduce Mn penetration into porous low-k when ALD MnN is used as the copper barrier.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"10 1","pages":"335-338"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80807185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Overview of embedded packaging technologies 嵌入式封装技术概述

2021 IEEE International Interconnect Technology Conference (IITC) Pub Date : 2014-05-20 DOI: 10.1109/IITC.2014.6831844

R. Pendse

{"title":"Overview of embedded packaging technologies","authors":"R. Pendse","doi":"10.1109/IITC.2014.6831844","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831844","url":null,"abstract":"Summary form only given. Moore's law has been the foundation for increasing complexity and density of semiconductor chips and has prevailed over the years through many transitions in silicon (Si) nodes. The simultaneous scaling of density, cost and performance which is made possible by fan-out wafer level packaging may be viewed as the manifestation of Moore's law in the packaging domain. Recent developments in Fan-out Wafer level technology (also known as embedded Wafer Level Ball Grid Array, or eWLB) at STATS ChipPAC ranging from package architecture, volume manufacturing processes, as well as comprehensive methodologies for defining the optimum application space for the packaging technology over competing options will be presented. Novel integration schemes comprising multi-die, 2.5D and 3D face-to-face configurations will be presented that enable a quantum leap in performance and form factor while being cost competitive to other alternative options such as Through Silicon Via (TSV). The proliferation of the application space from traditional RF and Base Band devices in Mobile products to more advanced Application Processors and larger packages in the computing space will be presented. The future direction for this technology, including new paradigms in manufacturing processes, will also be discussed.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"48 1","pages":"97-98"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75464577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Thermal stress control in Cu interconnects 铜互连中的热应力控制

2021 IEEE International Interconnect Technology Conference (IITC) Pub Date : 2014-05-20 DOI: 10.1109/IITC.2014.6831888

C. Yang, B. Li, F. Baumann, P. Wang, J. Li, R. Rosenberg, D. Edelstein

引用次数: 0

Foundry TSV integration and manufacturing challenges 代工TSV集成与制造挑战

2021 IEEE International Interconnect Technology Conference (IITC) Pub Date : 2014-05-20 DOI: 10.1109/IITC.2014.6831840

S. Gong, Wei Liu, Juan Boon Tan, Mahesh Bhatkar, H. Cong, J. Oswald, E. Lo, S. Siah

引用次数: 3