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2021 IEEE International Interconnect Technology Conference (IITC)最新文献

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Integration of a 3-D capacitor into a logic interconnect stack for high performance embedded DRAM SoC technology 将3-D电容器集成到逻辑互连堆栈中，用于高性能嵌入式DRAM SoC技术
2021 IEEE International Interconnect Technology Conference (IITC) Pub Date : 2014-05-20 DOI: 10.1109/IITC.2014.6831892
R. Brain, N. Bisnik, H.P. Chen, J. Neulinger, N. Lindert, J. Peach, L. Rockford, Y. Wang, K. Zhang
{"title":"Integration of a 3-D capacitor into a logic interconnect stack for high performance embedded DRAM SoC technology","authors":"R. Brain, N. Bisnik, H.P. Chen, J. Neulinger, N. Lindert, J. Peach, L. Rockford, Y. Wang, K. Zhang","doi":"10.1109/IITC.2014.6831892","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831892","url":null,"abstract":"A 22 nm generation technology is described incorporating transistor and interconnects with performance suitable for the needs of both high density DRAM and high-performance logic devices. We have integrated a 0.029 μm2 DRAM cell capable of meeting >100μs retention at 95°C. The process technology utilizes our leading edge 22nm 3-D tri-gate transistor as described previously [1-4]. We review the interconnect choices to enable the implementation of a high-aspect ratio 3-D capacitor into a SoC interconnect stack. Results will be reported for a test-vehicle with best-reported array density at 17.5Mb/mm2 based on a 128Mb macro in a 1Gbit eDRAM testchip [5].","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"54 1","pages":"299-302"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83235808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Challenges to via middle TSV integration at sub-28nm nodes 在亚28nm节点上通过中间TSV集成的挑战
2021 IEEE International Interconnect Technology Conference (IITC) Pub Date : 2014-05-20 DOI: 10.1109/IITC.2014.6831869
H. Kamineni, S. Kannan, R. Alapati, S. Thangaraju, Daniel Smith, Dingyou Zhang, Shan Gao
{"title":"Challenges to via middle TSV integration at sub-28nm nodes","authors":"H. Kamineni, S. Kannan, R. Alapati, S. Thangaraju, Daniel Smith, Dingyou Zhang, Shan Gao","doi":"10.1109/IITC.2014.6831869","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831869","url":null,"abstract":"This work presents the via middle TSV integration at sub-28 nm nodes using a new local interconnect scheme involving V0 vias. Various V0 schemes are presented along with their respective resistance, capacitance and leakage current data. The characterization and reliability results are presented through TSV daisy chain structures and MOL via chains.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"8 1","pages":"199-202"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82449454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Exploring alternative metals to Cu and W for interconnects: An ab initio insight 探索用于互连的铜和钨的替代金属:从头开始的见解
2021 IEEE International Interconnect Technology Conference (IITC) Pub Date : 2014-05-20 DOI: 10.1109/IITC.2014.6831868
K. Sankaran, S. Clima, M. Mees, C. Adelmann, Z. Tokei, G. Pourtois
{"title":"Exploring alternative metals to Cu and W for interconnects: An ab initio insight","authors":"K. Sankaran, S. Clima, M. Mees, C. Adelmann, Z. Tokei, G. Pourtois","doi":"10.1109/IITC.2014.6831868","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831868","url":null,"abstract":"The properties of alternative metals to Cu and W for interconnect applications are reviewed based on first-principles simulations and benchmarked in terms of intrinsic bulk resistivity and electromigration.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"4 1","pages":"193-196"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88902258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Switching and reliability mechanisms for ReRAM ReRAM的切换和可靠性机制
2021 IEEE International Interconnect Technology Conference (IITC) Pub Date : 2014-05-20 DOI: 10.1109/IITC.2014.6831832
Zhiqiang Wei, T. Ninomiya, S. Muraoka, K. Katayama, R. Yasuhara, T. Mikawa
{"title":"Switching and reliability mechanisms for ReRAM","authors":"Zhiqiang Wei, T. Ninomiya, S. Muraoka, K. Katayama, R. Yasuhara, T. Mikawa","doi":"10.1109/IITC.2014.6831832","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831832","url":null,"abstract":"Taking advantage of electron hopping between oxygen vacancies in filaments, ReRAM switching is caused by oxygen vacancy migration. We have developed an oxygen diffusion retention model, based on this switching mechanism, for both typical bits and outlier bits. Degradation of resistance of typical bits is due to the oxygen vacancy profile in the filament changing during oxygen diffusion, and the retention failure of outlier bits is caused by the critical percolation path being broken within the filament during oxygen diffusion.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"6 1","pages":"349-352"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73060138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A tri-axis MEMS capacitive sensor using multi-layered high-density metal for an integrated CMOS-MEMS accelerometer 一种采用多层高密度金属的三轴MEMS电容式传感器，用于集成CMOS-MEMS加速度计
2021 IEEE International Interconnect Technology Conference (IITC) Pub Date : 2014-05-20 DOI: 10.1109/IITC.2014.6831856
D. Yamane, T. Konishi, T. Matsushima, H. Toshiyoshi, K. Machida, K. Masu
{"title":"A tri-axis MEMS capacitive sensor using multi-layered high-density metal for an integrated CMOS-MEMS accelerometer","authors":"D. Yamane, T. Konishi, T. Matsushima, H. Toshiyoshi, K. Machida, K. Masu","doi":"10.1109/IITC.2014.6831856","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831856","url":null,"abstract":"This paper reports a novel tri-axis microelectro-mechanical systems (MEMS) capacitive sensor utilizing multi-layer electroplated gold. The high density of gold has enabled us to minimize the Brownian noise and hence to reduce the footprint of the proof mass. To optimize the flexibility of the mechanical springs for tri-axis motions, we have newly developed multi-layered metal spring structures. All the MEMS structures have been made by gold electroplating, used as a post complementary metal-oxide semiconductor (CMOS) process, and thereby the MEMS sensors can be implemented as integrated CMOS-MEMS accelerometers.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"26 1","pages":"113-116"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79497964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
HF etching mechanisms of advanced low-k films 先进低钾薄膜的HF刻蚀机理
2021 IEEE International Interconnect Technology Conference (IITC) Pub Date : 2014-05-20 DOI: 10.1109/IITC.2014.6831851
P. Verdonck, Q. Le, M. Krishtab, K. Vanstreels, S. Armini, A. Simone, M. Nguyen, M. Baklanov, S. Van Elshocht
{"title":"HF etching mechanisms of advanced low-k films","authors":"P. Verdonck, Q. Le, M. Krishtab, K. Vanstreels, S. Armini, A. Simone, M. Nguyen, M. Baklanov, S. Van Elshocht","doi":"10.1109/IITC.2014.6831851","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831851","url":null,"abstract":"Scaling of the Cu interconnect structures requires low-k materials which also have an adequate Young's modulus (e.g. E > 6 GPa) and good chemical resistance. This last characteristic can be determined through HF wet etching tests. In this paper, different types of low-k films (k-value range: 2.0-2.3; E range: 2 - 9 GPa) were immersed in a 0.5 volume % HF solution. The HF etching behaviour proved to be very dependent on the wetting properties of the film: even with lower Si-CH3 content, the film with highest water contact angle (i.e. most hydrophobic surface) was the most resistant against the HF etching.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"3 1","pages":"155-158"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80988949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of size effects in local interconnects for future technology nodes: A study based on full-chip layouts 未来技术节点局部互连尺寸效应的影响:基于全芯片布局的研究
2021 IEEE International Interconnect Technology Conference (IITC) Pub Date : 2014-05-20 DOI: 10.1109/IITC.2014.6831831
A. Ceyhan, Moongon Jung, Shreepad Panth, S. Lim, A. Naeemi
{"title":"Impact of size effects in local interconnects for future technology nodes: A study based on full-chip layouts","authors":"A. Ceyhan, Moongon Jung, Shreepad Panth, S. Lim, A. Naeemi","doi":"10.1109/IITC.2014.6831831","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831831","url":null,"abstract":"In this paper, we investigate the impact of local interconnect size effects on the performance of integrated circuits (ICs) based on timing-closed GDSII-level layouts of circuit blocks with detailed routing. For this purpose, we create multiple standard cell and interconnect libraries for 45-, 22-, 11- and 7-nm technology nodes considering scaling trends projected by the International Technology Roadmap for Semiconductors (ITRS) and assuming various sets of size effect parameters. We make comparisons between the performances of circuit designs that are implemented using these libraries.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"43 1","pages":"345-348"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87870982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Bottom-up copper deposition in alkaline electrolytes 碱性电解质中自下而上的铜沉积
2021 IEEE International Interconnect Technology Conference (IITC) Pub Date : 2014-05-20 DOI: 10.1109/IITC.2014.6831880
D. Josell, T. Moffat
{"title":"Bottom-up copper deposition in alkaline electrolytes","authors":"D. Josell, T. Moffat","doi":"10.1109/IITC.2014.6831880","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831880","url":null,"abstract":"Superconformal electrodeposition enables the fabrication of high aspect ratio interconnects that are ubiquitous in microelectronics. The Curvature Enhanced Accelerator Coverage (CEAC) mechanism captures the morphological and kinetic aspects of many “superfilling” processes for Damascene interconnect fabrication [1-4]. Present superfilling copper electrolytes are acidic. Alkaline chemistries might rely on a non-CEAC filling mechanism.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"306 1","pages":"281-284"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77017429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Synthesis and PEALD evaluation of new Nickel precursors 新型镍前驱体的合成及PEALD评价
2021 IEEE International Interconnect Technology Conference (IITC) Pub Date : 2014-05-20 DOI: 10.1109/IITC.2014.6831859
S. Gatineau, Changhee Ko, J. Gatineau, Clément Lansalot-Matras, Chang-Fang Hsiao
{"title":"Synthesis and PEALD evaluation of new Nickel precursors","authors":"S. Gatineau, Changhee Ko, J. Gatineau, Clément Lansalot-Matras, Chang-Fang Hsiao","doi":"10.1109/IITC.2014.6831859","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831859","url":null,"abstract":"A new family of oxygen and fluorine free Nickel (Ni) precursors, which are based on allyl and alkylpyrrolylimine ligands [Ni(allyl)(PCAI-R)], has been developed and evaluated for a Ni metal film with thermal and plasma enhanced ALD using H<sub>2</sub>/NH<sub>3</sub> as a reducing agent. From Ni(allyl)(PCAI-iPr), pure Ni film with very low resistivity (5.3 μO·cm) was obtained at 400°C by PEALD, which is close to the resistivity value of bulk Nickel (5-10 μO·cm) [1].","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"24 1","pages":"125-126"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84485849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A self-aligned via etch process to increase yield and reliability of 90 nm pitch critical interconnects with ultra-thin TiN hardmask 采用超薄TiN硬掩膜的自对准蚀刻工艺，提高90 nm间距关键互连的良率和可靠性
2021 IEEE International Interconnect Technology Conference (IITC) Pub Date : 2014-05-20 DOI: 10.1109/IITC.2014.6831860
J. Liao, Y. T. Lai, B. Kuo, P. Gopaladasu, Scott Wang, S. Yao, Kiki Wang, I. Wang, Paul Lin, Barrett Finch, S. Deshmukh
{"title":"A self-aligned via etch process to increase yield and reliability of 90 nm pitch critical interconnects with ultra-thin TiN hardmask","authors":"J. Liao, Y. T. Lai, B. Kuo, P. Gopaladasu, Scott Wang, S. Yao, Kiki Wang, I. Wang, Paul Lin, Barrett Finch, S. Deshmukh","doi":"10.1109/IITC.2014.6831860","DOIUrl":"https://doi.org/10.1109/IITC.2014.6831860","url":null,"abstract":"Back-end-of line (BEOL) interconnect scaling has led to the implementation of self-aligned via (SAV) schemes for ≤ 90 nm BEOL pitches [1]. In one implementation of this scheme, a TiN metal hardmask (MHM) is used for the trench pattern definition while the interconnect vias are patterned using a tri-layer resist mask such that the vias are self-aligned to the underlayer trench lines [2]. In this work, we describe a SAV etch process that enables the use of thin (≤ 15 nm) TiN MHM. Key attributes of the via and trench etching process in a capacitively coupled etch reactor are described to meet physical performance requirements and eliminate tradeoffs between via chain yield and via-to-metal (M2-V1) bridging. Low-k sidewall damage, post-etch wet clean, and metallization are discussed. Finally, the physical etch performance is correlated to the device breakdown voltage (VBD) and time-dependent dielectric breakdown (TDDB) lifetime performance.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"33 1","pages":"127-130"},"PeriodicalIF":0.0,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80233395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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