嵌入式封装技术概述

R. Pendse
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引用次数: 1

摘要

只提供摘要形式。摩尔定律一直是增加半导体芯片复杂性和密度的基础,并在硅(Si)节点的许多转变中盛行多年。通过扇形圆片级封装实现的密度、成本和性能的同时缩放可以看作是摩尔定律在封装领域的体现。在STATS ChipPAC上,扇形外展晶圆级技术(也称为嵌入式晶圆级球栅阵列,或eWLB)的最新发展,包括封装架构,批量制造工艺,以及在竞争选项中定义封装技术最佳应用空间的综合方法。包括多芯片、2.5D和3D面对面配置在内的新型集成方案将在性能和外形方面实现巨大飞跃,同时与其他替代方案(如通硅通孔(TSV))相比具有成本竞争力。从移动产品中的传统射频和基带设备到计算空间中更先进的应用处理器和更大的封装的应用空间的扩散将被呈现。该技术的未来方向,包括制造工艺的新范式,也将被讨论。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Overview of embedded packaging technologies
Summary form only given. Moore's law has been the foundation for increasing complexity and density of semiconductor chips and has prevailed over the years through many transitions in silicon (Si) nodes. The simultaneous scaling of density, cost and performance which is made possible by fan-out wafer level packaging may be viewed as the manifestation of Moore's law in the packaging domain. Recent developments in Fan-out Wafer level technology (also known as embedded Wafer Level Ball Grid Array, or eWLB) at STATS ChipPAC ranging from package architecture, volume manufacturing processes, as well as comprehensive methodologies for defining the optimum application space for the packaging technology over competing options will be presented. Novel integration schemes comprising multi-die, 2.5D and 3D face-to-face configurations will be presented that enable a quantum leap in performance and form factor while being cost competitive to other alternative options such as Through Silicon Via (TSV). The proliferation of the application space from traditional RF and Base Band devices in Mobile products to more advanced Application Processors and larger packages in the computing space will be presented. The future direction for this technology, including new paradigms in manufacturing processes, will also be discussed.
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